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2016-05-24Remove FSF address from GPL noticesMarc Schink1-3/+1
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-20Fix spelling of ARM CortexAndreas Färber1-1/+1
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn or CortexXn. Further it's Cortex-M0+, not M0plus. Cf. http://www.arm.com/products/processors/index.php Consistently write it the official way, so that it stops propagating. Originally spotted in the documentation, it mainly affects code comments but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output. Found via: git grep -i "Cortex " git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu" git grep -i "CortexM" Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3483 Tested-by: jenkins Reviewed-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-06Cortex-M7: Give user a hint about single stepping problem up to r0p1.Uwe Bonnes1-0/+7
http://www.keil.com/support/docs/3778.htm Change-Id: I452f76726f3bb269fa14cc785f329bfba5189489 Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/3467 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2016-05-05target: improve robustness of reset commandTomas Vanek1-31/+26
Before this change jim_target_reset() checked examined state of a target and failed without calling .assert_reset in particular target layer (and without comprehensible warning to user). Cortex-M target (which refuses access to DP under active SRST): If connection is lost then reset process fails before asserting SRST and connection with MCU is not restored. This resulted in: 1) A lot of Cortex-M MCUs required use of reset button or cycling power after firmware blocked SWD access somehow (sleep, misconfigured clock etc). If firmware blocks SWD access early during initialization, a MCU could become completely inaccessible by SWD. 2) If OpenOCD is (re)started and a MCU is in a broken state unresponsive to SWD, reset command does not work even if it could help to restore communication. Hopefully this scenario is not possible under full JTAG. jim_target_reset() in target.c now does not check examined state and delegates this task to a particular target. All targets have been checked and xx_assert_reset() (or xx_deassert_reset()) procedures were changed to check examined state if needed. Targets except arm11, cortex_a and cortex_m just fail if target is not examined although it may be possible to use at least hw reset. Left as TODO for developers familiar with these targets. cortex_m_assert_reset(): memory access errors are stored instead of immediate returning them to a higher level. Errors from less important reads/writes are ignored. Requested reset always leads to a configured action. arm11_assert_reset() just asserts hw reset in case of not examined target. cortex_a_assert_reset() works as usual in case of not examined target. Change-Id: I84fa869f4f58e2fa83b6ea75de84440d9dc3d929 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/2606 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-12-30target: cortex_m: fix segfault with HLAPaul Fertser1-17/+17
The HLA target shares an examine handler with cortex_m but since it lacks direct access to DAP, some operations need to be omitted. Change-Id: Ifdd9d3da4a3a3c2e1c9721284b21d041b3ccaa7a Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3183 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-29cortex: Set default memaccess_tck only during examineAndreas Fritiofson1-3/+0
It's currently set during target creation but the AP that will be used for the target is not even known. Change-Id: I4502e7eb1fa8d90f746445b8cf8a4c21cb7d519e Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3155 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Remove all mem_ap_sel_* functionsAndreas Fritiofson1-52/+52
All mem_ap_* functions now make sure the SELECT register is updated with the AP number that it's operating on. This shouldn't have to be handled explicitly. Change-Id: Ib193d8930fabb6a25715064355f98258c9580b5d Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3153 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Split ahbap_debugport_initAndreas Fritiofson1-3/+9
This function does two separate things, powering up the DP and setting up a MEM-AP. But the DP needs to be powered before even searching for a MEM-AP to initialize and targets may have multiple MEM-APs that need initializing. Split the function into dap_dp_init() and mem_ap_init() and change all call sites to use the appropriate one. Change-Id: I92f55e09754a93f3f01dd8e5aa1ffdf60c856126 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3151 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Change mem_ap calls to take pointer to AP and not DAPAndreas Fritiofson1-69/+55
Change-Id: I8d3e42056aa5828cb917ca578a54b7d53846a150 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3149 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Convert the AP references from numbers to pointersAndreas Fritiofson1-57/+57
Change the debug_ap and memory_ap fields of the cortex_a target and the debug_ap field of the cortex_m target to be pointers to the struct adiv5_ap instead of AP numbers in some known DAP. This reduces the dependency on the DAP struct in the targets and enables MEM-AP accesses to take the relevant AP as parameter. Change-Id: I39d7b134d78000564b7eec5bff464adf0ef89147 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3147 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29cortex_m: Discover the AP to use, just like Cortex-AAndreas Fritiofson1-0/+7
This required fixing the AP ID parsing in dap_find_ap() to match IHI0031C. The AXI type was added too. Change-Id: I44577a7848df37586e650dce0fb57ac26f5f858c Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3146 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29target/arm: Remove usage of struct arm_jtag in ARMv7 targetsAndreas Fritiofson1-10/+1
The Cortex-A and Cortex-M keeps an arm_jtag struct around just to be able to pass a pointer to it to one common JTAG function which anyway only uses the TAP field. Refactor the function to take a TAP directly, remove the legacy struct from cortex instances and store the TAP pointer only in the DAP. Cortex-M makes a call to arm_jtag_setup_connection() with the struct but the function does nothing useful for a Cortex-M target so remove the call. Change-Id: I3b33709ef55372ef14522ed4337e9f2e817ae3ab Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3142 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_debug: Support multiple APs per DAP and remove DAP from armv7* structsPatrick Stewart1-12/+17
Separate out the values from adiv5_dap that are associated with a specific AP into a new struct, so we can properly support multiple APs. Remove the DAP struct from the armv7* structs, because we can have multiple CPUs per DAP, and we shouldn't have multiple DAP structs. Tidy up a few places where ap_current is used incorrectly. Change-Id: I0c6ef4b49cc86b140366347aaf9b76c07cbab0a8 Signed-off-by: Patrick Stewart <patstew@gmail.com> Reviewed-on: http://openocd.zylin.com/2984 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-29cortex_m: Select an AP when accessing the DAPPatrick Stewart1-55/+63
Prepare to support multiple cortex-m cores on one DAP. Uses mem_ap_sel_* functions and removes mem_ap_* functions. Adds a new debug_ap parameter to the cortex_m (currently set to zero as in existing code). Change-Id: I6926029d1e7bf44a42d453d1aff349bda824ba72 Signed-off-by: Patrick Stewart <patstew@gmail.com> Reviewed-on: http://openocd.zylin.com/2983 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-11-03cortex_m: dwt_num_comp should be set to zero in cortex_m_dwt_free()Tomas Vanek1-0/+1
A segmentation fault in cortex_m_endreset_event() is sometimes raised with very broken target like Kinetis Kx with erased flash and active WDOG. Debugging revealed that cortex_m->dwt_num_comp is 4 and dwt_list is NULL at cortex_m:290 Change-Id: I229c59d6da13d816df513d1dbb19968e4b5951e2 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/2989 Reviewed-by: Thomas Schmid <thomas@rfranging.com> Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-10-30Cortex-M: Detect Flash Patch Revision and implement Rev. 2 handling.Uwe Bonnes1-3/+14
E.g. STM32F7 implements Rev.2. Supercedes abandoned patch 2755 that doesn't evaluate Flash patch revision. Change-Id: I48756b0451c7359475066969c900978a536bc328 Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/2868 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-09-30armv7m: Fix memory leak in register caching.Marc Schink1-1/+8
Change-Id: I184042d277a52f3940d6d6c13f3d94afc557933d Signed-off-by: Marc Schink <openocd-dev@marcschink.de> [andreas.fritiofson@gmail.com: don't check pointers before free()] Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/2881 Tested-by: jenkins
2015-04-14target/arm_adi_v5, cortex_m: retry ahbap_debugport_init few times in case of ↵Paul Fertser1-0/+11
an error Some targets need arbitrary amount of time (usually not too long) after reset (both sysresetreq and srst) to do initialisation, and SWD/JTAG is not available during that. According to PSoC4 docs, the debugger should try connecting until it succeeds. Also ahbap_debugport_init might be necessary to perform after using hardware srst too, so add it there (except for the targets that support srst_nogate since they are very unlikely to need it). Change-Id: I3598d5ff7b8e0bf3a5566a57dec4b0b2b243d297 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2601 Tested-by: jenkins
2015-03-25target/adi_v5_swd, cortex_m: properly handle more cases requiring reconnectPaul Fertser1-16/+9
This brings SWD reconnection procedure in line with the ARM documentation and changes cortex_m reset procedure to make use of it. The motivation behind this patch is to make SAM4L "reset" and "reset halt" properly without SRST. The complication here is that EDBG issues an additional read of DP_RDBUFF automatically right after writing SYSRESETREQ, that leads to a FAULT which needs to be dealt with properly. With this patch the very first ahbap_debugport_init DAP access will make SWD layer properly reinitialise the link before continuing. Runtime tested with mbed CMIS-DAP + KL25 only. Change-Id: Ic506f9db30931dfa60860036b83f73b897975909 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2596 Tested-by: jenkins Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-03-25armv7m: add generic trace support (TPIU, ITM, etc.)Paul Fertser1-0/+13
This provides support for various trace-related subsystems in a generic and expandable way. Change-Id: I3a27fa7b8cfb111753088bb8c3d760dd12d1395f Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2538 Tested-by: jenkins
2015-03-09server, target, cortex_m: add deinit_target to the API to free resourcesPaul Fertser1-0/+10
This should facilitate dynamic target creation and removal. Currently it helps with getting 0 bytes lost report from Valgrind on exit (after talking to a nucleo board). However, 1,223,886 bytes in 5,268 blocks are still reachable which means the app holds pointers to that data on exit. The majority comes from the jtag command queue, there're also many blocks from TCL command registration. Change-Id: I7523234bb90fffd26f7d29cdd7648ddd221d46ab Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2544 Tested-by: jenkins Reviewed-by: Stian Skjelstad <stian@nixia.no>
2015-03-09target/cortex_m: do not leak memory on reexaminationPaul Fertser1-0/+24
This bug was exposed by Valgrind. Change-Id: If50878664d928c0a44e309ca1452089c1ac71466 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2542 Tested-by: jenkins Reviewed-by: Stian Skjelstad <stian@nixia.no> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-03-09armv7m: do not access FPU registers when not presentPaul Fertser1-0/+11
This is runtime and valgrind tested with l0, l1 and f3 hla boards. Change-Id: I49b0b042253d5f3bf216997f0203583db319fe23 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2516 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-03-09armv7m: add FPU registers supportPaul Fertser1-0/+46
This patch adds the fpv4-sp-d16 registers to the armv7m register set. The work is inspired by Mathias K but takes a different approach: instead of having both double and single presicion registers in the cache this patch works only with the doubles and counts on GDB to split the data in halves whenever needed. Tested with HLA only (on an STM32F334 disco board). Currently this patch makes all ARMv7-M targets report an FPU-enabled target description to GDB. It shouldn't harm if the user is not trying to access non-existing FPU. However, the plan is to make this depend on actual FPU presence later. Change-Id: Ifcc72c80ef745230c42e4dc3995f792753fc4e7a Signed-off-by: Mathias K <kesmtp@freenet.de> [fercerpav@gmail.com: rework to fit target description framework] Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/514 Tested-by: jenkins Reviewed-by: Peter Stuge <peter@stuge.se> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-02-11cortex_m: Use the correct method to access registersAndreas Fritiofson1-4/+10
Convert the DWT register store to use a byte array and fix the byte order bug uncovered by that. Also fix an incorrect access of the PC value. Change-Id: Idb5acab71bdf5a96895c358324b05c335e4d32ca Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/2476 Tested-by: jenkins Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2014-09-29cortex_m.c: Use two byte breakpoint for 32bit Thumb-2 requestJon Burgess1-0/+5
When GDB requests a breakpoint on a 32bit Thumb-2 instruction it sends a length of 3 which the current code rejects. Using the existing two byte breakpoint for this case appears to work fine. The use of length==3 for this case is mentioned in a few places: https://sourceware.org/gdb/onlinedocs/gdb/ARM-Breakpoint-Kinds.html http://sourceforge.net/p/openocd/mailman/message/30012280/ Change-Id: I59cd69ba4d1bc9a37b86569738c6bb2a67c3eb7a Signed-off-by: Jon Burgess <jburgess777@gmail.com> Reviewed-on: http://openocd.zylin.com/2312 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-09-15cortex_m: Check return value from cortex_m_dcc_read.Andreas Fritiofson1-8/+13
Caught by clang. Change-Id: I26d2b845aca431612862ef432b217ca397d9b893 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/2279 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-06-28Add error handling and remove double readout.Mathias K1-10/+7
Remove double readout of DCB_DHCSR in target poll. The return value of the endreset event is handled and not ignored in target poll. Change-Id: I8fe026418dadcf0b0dcbb09acee871ad950937a2 Signed-off-by: Mathias K <kesmtp@freenet.de> Reviewed-on: http://openocd.zylin.com/1181 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2014-06-28cortex_m: Do additional initialization during resetAndrey Smirnov1-0/+13
SAM4L requires additional steps to be taken right after SYSRESETREQ is issued in order to function robustly: - CMSIS-DAP DAP driver needs to explicitly check for sticky bit errors since it is possible for adapter to perform successful write opration, report no errors and then, under the hood, do some other things that will result in sticky bit being set. - Debugger needs to wait for security system to finish intialization and assert CDBGPWRUPACK before proceeding This change is related to commit http://openocd.zylin.com/#/c/1995/ Change-Id: I741c95a809bfd60d930cec9482239e4796a62326 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-on: http://openocd.zylin.com/2088 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com>
2014-01-19cortexm: use Cortex-M rather than cortex-m3 for dwt registersSpencer Oliver1-1/+1
Change-Id: I28e3a8c65ccc4a4e3ec94e41c846e6a263c165e8 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1865 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2014-01-11cortex_m: Avoid unnecessary saving and restoring of DCRDRAndreas Fritiofson1-54/+37
This is used for the emulated DCC channel which is only maintained as long as target->dbg_msg_enabled is set. Skip the saving and restoring if not enabled to save one dap_run() per core register access. Note that we could've probably queued all core register accesses in the same transaction if the armv7 register framework hadn't required synchronous register accesses. Change-Id: I4fe6d713261ee5db42422203eb63035fdcc48891 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1848 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-01-11cortex_m: Fix possible endianness problem in emulated DCC channelAndreas Fritiofson1-13/+16
Change-Id: If7104464a8c65085f3ceac445e9c9be8446f2da9 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1846 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-31Clean up many C99 integer types format specifiersPaul Fertser1-4/+4
This eliminates most of the warnings reported when building for arm-none-eabi (newlib). Hsiangkai, there're many similar warnings left in your nds32 files, I didn't have the nerve to clean them all, probably you could pick it up. Change-Id: Id3bbe2ed2e3f1396290e55bea4c45068165a4810 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1674 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-29cortex_m: set fpb_enabled on enabling fpbSpencer Oliver1-3/+29
If the fpb_enabled is not set then as part of cortex_m3_set_breakpoint we enable the fpb, however we do not signal the fpb as being enabled. This issue only effects the hla target as the current cortex_m code enables the fpb during cortex_m3_endreset_event. Change-Id: I44d3fc65916c131b7a226869dd16aed5afb441b4 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1634 Tested-by: jenkins
2013-10-10cortex_m: target implementation renames cortex_m3 to cortex_mSpencer Oliver1-300/+297
We changed the actual target name quite a while ago. This changes the actual target function names/defines to also match this change. Change-Id: I4f22fb107636db2279865b45350c9c776e608a75 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1626 Tested-by: jenkins
2013-10-02cortex_m: Call mem_ap_read/write directlyAndreas Fritiofson1-33/+2
Change-Id: I52e1d8babf7bf9fcde4094046d29b817c15c0562 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1659 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-02cortex_m: mem_ap access functions take number of bytes, not wordsAndreas Fritiofson1-2/+2
Accessing one byte of memory using a 16-bit access is not well defined. The current implementation is forgiving and rounds up, but it should not be relied upon. Also, I suspect this code might fail if the byte order differs between target and host, but I have no way of verifying it so I left it as it is. Change-Id: I8d6a511151a194ed419f141703201f0632d84fc8 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1657 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-09-21armv7m: remove gdb register hacksSpencer Oliver1-33/+1
Now that we support the target description format we do not need these hacks anymore, we can now tell gdb what registers we support. Change-Id: Ie774231d296420b35efcf708bc4435475c87ff5e Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1617 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-09-08armv7m: use consistent arm.cpsr memberSpencer Oliver1-2/+2
We already set cpsr in armv7m_build_reg_cache, so lets use it for all other accesses to this field. Change-Id: I19b3b21ecf1571bbea12e1be664845e6544f6fa1 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1539 Tested-by: jenkins
2013-07-26cortex_m: change cmd output to use cortex_m rather than cortex_m3Spencer Oliver1-3/+3
Change-Id: I33834910c44d22169bcf684e9697a8db49d0b396 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1513 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-07-01cortex_m: deprecate soft_reset_haltSpencer Oliver1-0/+6
soft_reset_halt was only really intended for the older arm arch, eg. armv4/5. Newer arch such as armv7m/mips do not need this as they have better alternatives. Change-Id: Ifb360680b7e4bfa5365f3c79d82574bded952b45 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1442 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-06-05update files to correct FSF addressSpencer Oliver1-1/+1
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2013-06-03cortex_m: print 'Cortex-M' rather than 'Cortex-M3'Spencer Oliver1-3/+3
This file is used by all the Cortex-M family not just Cortex-M3. Change-Id: Ie8680535b220c66bb8fcd862510407a46a73e8a0 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1429 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-05-29cortex_m, hla_target: do not try asserting SRST if it's not presentPaul Fertser1-1/+2
This should cover all the cases when RESET_SRST_NO_GATING is set without RESET_HAS_SRST. This might happen when RESET_SRST_NO_GATING is automatically set by a target code (and not from tcl). However, there're some other places (mips_m4k, arm7_9_common) where adding RESET_SRST_PULLS_TRST would lead to trying to use SRST even if it's not present. Currently it's impossible for the user to enable that flag without enabling SRST. Change-Id: Ib1c6f68feed0b8057d55afd5f260bb22ab332ced Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1405 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-28target: rename cortex_m3 to cortex_mSpencer Oliver1-3/+4
Rename cortex_m3 target to use a more correct cortex_m name. This also adds a deprecated_name var so that older scripts issue a warning to update the target name. cfg files have also been updated to the new target name. Change-Id: Ia8429f38e88da677249c5caa560c50f8ce56ea10 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1129 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-28cortex_m: remove old target breakpoints/watchpointsSpencer Oliver1-0/+6
Sometimes the target may have breakpoint registers set from a previous debug session, we can either sync them or as we have chosen here clear them. Change-Id: I439a623ebbf010246a70e5596d04aa7d546da731 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1363 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-03-15target: Add default implementation of bulk_write_memoryAndreas Fritiofson1-7/+0
Remove dummy implementations from all targets except arm7_9 and mips, which are the only ones with real implementations. Replace with a single default implementation simply calling target_write_memory(). Change-Id: I9228104240bc0b50661be20bc7909713ccda2164 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1213 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15cortex_a : optimize apb read/write access.Evan Hunter1-2/+2
Rewrite: Adheres more closely to 'fast read/write' examples in TRM. up to 50x faster Change-Id: Ieb4da57d8367628f3e7306827a5b1f0ab550e641 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/903 Tested-by: jenkins Reviewed-by: Michel JAOUEN <michel.jaouen@stericsson.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-02-02armv7m: use generic arm read/write_core_regSpencer Oliver1-2/+3
Change-Id: I0c15acc1278d2972269d294078495e6b069c830b Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/969 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: use generic register core_cacheSpencer Oliver1-13/+13
This removes the armv7m::core_cache and uses the generic arm::core_cache. Change-Id: If854281b31486cea8be005008f6a71a691b4c208 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/968 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
generated by cgit v1.1 at 2024-08-19 12:34:42 +0000