diff options
| author | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2015-01-18 15:34:42 +0100 |
|---|---|---|
| committer | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2015-02-11 22:16:57 +0000 |
| commit | 24e99ac6d9a8a7672da832ec54e015b66aef246c (patch) | |
| tree | 6115a0428631a62acc20e043ca9f5cd6562b6ddd /src/target/cortex_m.c | |
| parent | 0ecb0396d4ddfcfb8c499a0fba5ccc929100e000 (diff) | |
| download | riscv-openocd-24e99ac6d9a8a7672da832ec54e015b66aef246c.zip riscv-openocd-24e99ac6d9a8a7672da832ec54e015b66aef246c.tar.gz riscv-openocd-24e99ac6d9a8a7672da832ec54e015b66aef246c.tar.bz2 | |
cortex_m: Use the correct method to access registers
Convert the DWT register store to use a byte array and fix the byte order
bug uncovered by that. Also fix an incorrect access of the PC value.
Change-Id: Idb5acab71bdf5a96895c358324b05c335e4d32ca
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2476
Tested-by: jenkins
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Diffstat (limited to 'src/target/cortex_m.c')
| -rw-r--r-- | src/target/cortex_m.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index a5230b7..d3b8f4e 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -473,7 +473,7 @@ static int cortex_m_debug_entry(struct target *target) LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s", arm_mode_name(arm->core_mode), - *(uint32_t *)(arm->pc->value), + buf_get_u32(arm->pc->value, 0, 32), target_state_name(target)); if (armv7m->post_debug_entry) { @@ -1646,14 +1646,20 @@ static int cortex_m_init_target(struct command_context *cmd_ctx, struct dwt_reg_state { struct target *target; uint32_t addr; - uint32_t value; /* scratch/cache */ + uint8_t value[4]; /* scratch/cache */ }; static int cortex_m_dwt_get_reg(struct reg *reg) { struct dwt_reg_state *state = reg->arch_info; - return target_read_u32(state->target, state->addr, &state->value); + uint32_t tmp; + int retval = target_read_u32(state->target, state->addr, &tmp); + if (retval != ERROR_OK) + return retval; + + buf_set_u32(state->value, 0, 32, tmp); + return ERROR_OK; } static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf) @@ -1708,7 +1714,7 @@ static void cortex_m_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg r->name = d->name; r->size = d->size; - r->value = &state->value; + r->value = state->value; r->arch_info = state; r->type = &dwt_reg_type; } |