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| author | Paul Fertser <fercerpav@gmail.com> | 2015-01-29 13:58:45 +0300 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2015-03-09 06:36:49 +0000 |
| commit | 217403ce096627fec035b79f9464e5bfc09e8f06 (patch) | |
| tree | c012ce202cd9cd70b970ef47c45a23b4d1bd5107 /src/target/cortex_m.c | |
| parent | dccbf7d88d05a1f7a22f164ef149777718a399ed (diff) | |
| download | riscv-openocd-217403ce096627fec035b79f9464e5bfc09e8f06.zip riscv-openocd-217403ce096627fec035b79f9464e5bfc09e8f06.tar.gz riscv-openocd-217403ce096627fec035b79f9464e5bfc09e8f06.tar.bz2 | |
armv7m: do not access FPU registers when not present
This is runtime and valgrind tested with l0, l1 and f3 hla boards.
Change-Id: I49b0b042253d5f3bf216997f0203583db319fe23
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2516
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/target/cortex_m.c')
| -rw-r--r-- | src/target/cortex_m.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index b194c33..38ed4c3 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -1885,6 +1885,17 @@ int cortex_m_examine(struct target *target) armv7m->arm.is_armv6m = true; } + if (armv7m->fp_feature != FPv4_SP && + armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) { + /* free unavailable FPU registers */ + size_t idx; + for (idx = ARMV7M_NUM_CORE_REGS_NOFP; + idx < armv7m->arm.core_cache->num_regs; + idx++) + free(armv7m->arm.core_cache->reg_list[idx].value); + armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP; + } + if (i == 4 || i == 3) { /* Cortex-M3/M4 has 4096 bytes autoincrement range */ armv7m->dap.tar_autoincr_block = (1 << 12); |