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| author | Paul Fertser <fercerpav@gmail.com> | 2015-03-11 11:33:55 +0300 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2015-03-25 21:32:06 +0000 |
| commit | 492bab62abe6e94a302899ed19af7e1b23365e78 (patch) | |
| tree | 7ff29fdc43fb0a831bd22a962095396060bfe928 /src/target/cortex_m.c | |
| parent | ef02b69b14d133b061217a91add5a028a77e86bc (diff) | |
| download | riscv-openocd-492bab62abe6e94a302899ed19af7e1b23365e78.zip riscv-openocd-492bab62abe6e94a302899ed19af7e1b23365e78.tar.gz riscv-openocd-492bab62abe6e94a302899ed19af7e1b23365e78.tar.bz2 | |
target/adi_v5_swd, cortex_m: properly handle more cases requiring reconnect
This brings SWD reconnection procedure in line with the ARM
documentation and changes cortex_m reset procedure to make use of it.
The motivation behind this patch is to make SAM4L "reset" and "reset
halt" properly without SRST. The complication here is that EDBG issues
an additional read of DP_RDBUFF automatically right after writing
SYSRESETREQ, that leads to a FAULT which needs to be dealt with
properly. With this patch the very first ahbap_debugport_init DAP
access will make SWD layer properly reinitialise the link before
continuing.
Runtime tested with mbed CMIS-DAP + KL25 only.
Change-Id: Ic506f9db30931dfa60860036b83f73b897975909
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2596
Tested-by: jenkins
Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/target/cortex_m.c')
| -rw-r--r-- | src/target/cortex_m.c | 25 |
1 files changed, 9 insertions, 16 deletions
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 9234824..3e42af0 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -1053,12 +1053,6 @@ static int cortex_m_assert_reset(struct target *target) * This has the disadvantage of not resetting the peripherals, so a * reset-init event handler is needed to perform any peripheral resets. */ - retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, - AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ) - ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET)); - if (retval != ERROR_OK) - return retval; - LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ) ? "SYSRESETREQ" : "VECTRESET"); @@ -1067,17 +1061,16 @@ static int cortex_m_assert_reset(struct target *target) "handler to reset any peripherals or configure hardware srst support."); } - /* - SAM4L needs to execute security initalization - startup sequence before AP access would be enabled. - During the intialization CDBGPWRUPACK is pulled low and we - need to wait for it to be set to 1 again. - */ - retval = dap_dp_poll_register(swjdp, DP_CTRL_STAT, - CDBGPWRUPACK, CDBGPWRUPACK, 100); + retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, + AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ) + ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET)); + if (retval != ERROR_OK) + LOG_DEBUG("Ignoring AP write error right after reset"); + + retval = ahbap_debugport_init(swjdp); if (retval != ERROR_OK) { - LOG_ERROR("Failed waitnig for CDBGPWRUPACK"); - return ERROR_FAIL; + LOG_ERROR("DP initialisation failed"); + return retval; } { |