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authorSpencer Oliver <spen@spen-soft.co.uk>2013-09-11 12:33:32 +0100
committerAndreas Fritiofson <andreas.fritiofson@gmail.com>2013-09-21 20:08:38 +0000
commit80a94681de4c304ed8d550d4da547cdc523d2207 (patch)
tree45e9403d4a5b9f88d71d183768469b86b8e07186 /src/target/cortex_m.c
parentd14058db0aee78de9a9bc5bddeafe7844ac01587 (diff)
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armv7m: remove gdb register hacks
Now that we support the target description format we do not need these hacks anymore, we can now tell gdb what registers we support. Change-Id: Ie774231d296420b35efcf708bc4435475c87ff5e Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1617 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Diffstat (limited to 'src/target/cortex_m.c')
-rw-r--r--src/target/cortex_m.c34
1 files changed, 1 insertions, 33 deletions
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index fbe635b..5892a0e 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -433,17 +433,6 @@ static int cortex_m3_debug_entry(struct target *target)
r = arm->cpsr;
xPSR = buf_get_u32(r->value, 0, 32);
-#ifdef ARMV7_GDB_HACKS
- /* FIXME this breaks on scan chains with more than one Cortex-M3.
- * Instead, each CM3 should have its own dummy value...
- */
- /* copy real xpsr reg for gdb, setting thumb bit */
- buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
- buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
- armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
- armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
-#endif
-
/* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
if (xPSR & 0xf00) {
r->dirty = r->valid;
@@ -1232,17 +1221,8 @@ int cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoin
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- if (cortex_m3->auto_bp_type) {
+ if (cortex_m3->auto_bp_type)
breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
-#ifdef ARMV7_GDB_HACKS
- if (breakpoint->length != 2) {
- /* XXX Hack: Replace all breakpoints with length != 2 with
- * a hardware breakpoint. */
- breakpoint->type = BKPT_HARD;
- breakpoint->length = 2;
- }
-#endif
- }
if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
if (breakpoint->type == BKPT_HARD) {
@@ -1540,18 +1520,6 @@ static int cortex_m3_store_core_reg_u32(struct target *target,
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = armv7m->arm.dap;
-#ifdef ARMV7_GDB_HACKS
- /* If the LR register is being modified, make sure it will put us
- * in "thumb" mode, or an INVSTATE exception will occur. This is a
- * hack to deal with the fact that gdb will sometimes "forge"
- * return addresses, and doesn't set the LSB correctly (i.e., when
- * printing expressions containing function calls, it sets LR = 0.)
- * Valid exception return codes have bit 0 set too.
- */
- if (num == ARMV7M_R14)
- value |= 0x01;
-#endif
-
/* NOTE: we "know" here that the register identifiers used
* in the v7m header match the Cortex-M3 Debug Core Register
* Selector values for R0..R15, xPSR, MSP, and PSP.