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path: root/src/priv-preface.tex
AgeCommit message (Expand)AuthorFilesLines
2020-07-22Pmp wording fix (#545)Stef O'Rear1-1/+1
2020-06-10Fix prefaceAndrew Waterman1-2/+2
2020-06-10Priority of misaligned load/store address checks is implementation-definedAndrew Waterman1-0/+3
2020-05-22Extend PMP scheme to support 64 regionsAndrew Waterman1-0/+1
2020-03-23PMP reset values are now platform-definedAndrew Waterman1-0/+1
2020-02-08Update hypervisor spec to v0.6Andrew Waterman1-1/+1
2019-11-20Update prefaceAndrew Waterman1-12/+22
2019-11-19MRET and SRET clear MPRV when leaving M-modeAndrew Waterman1-0/+1
2019-11-07Reserve satp fields when MODE=BareAndrew Waterman1-0/+1
2019-10-29hypervisor draft v0.5Andrew Waterman1-1/+1
2019-10-02Incorporate some of #416 and #418Andrew Waterman1-2/+2
2019-10-02Incorporate Dan's feedbackAndrew Waterman1-2/+2
2019-10-02More LR/SC updatesAndrew Waterman1-0/+2
2019-09-28Update prefaceAndrew Waterman1-0/+1
2019-08-27scause must be able to hold the values 0-31Andrew Waterman1-0/+2
2019-08-26Relaxed I/O adheres to Appendix A 4.2archiveAndrew Waterman1-0/+3
2019-07-21Move N extension into its own chapter in the priv specAndrew Waterman1-0/+1
2019-06-21Fix preface styleAndrew Waterman1-2/+2
2019-06-21Add mstatush to prefaceAndrew Waterman1-0/+2
2019-06-19Add endianness control proposal to priv specAndrew Waterman1-0/+1
2019-06-16Bump priv spec to v1.12-draftAndrew Waterman1-4/+38
2019-06-08Added text to indicate this is the ratified 1.11 version of the spec.Ratified-IMFDQC-and-Priv-v1.11Krste Asanovic1-4/+5
2019-04-11forgot to bump hypervisor spec draft versionAndrew Waterman1-1/+1
2019-03-26Add preface entry for mcountinhibit CSRAndrew Waterman1-0/+2
2019-03-12Specify synchronous exception priority orderingAndrew Waterman1-0/+1
2019-03-07Update prefaceAndrew Waterman1-0/+1
2019-03-07Add software constraint for future global-ASID extensionAndrew Waterman1-0/+4
2018-12-02Remove PLIC chapter from privileged specAndrew Waterman1-0/+1
2018-12-02Update privileged prefaceAndrew Waterman1-2/+23
2018-12-02Clarify misaligned-AMO emulation schemeAndrew Waterman1-3/+1
2018-11-30Update prefaceAndrew Waterman1-0/+2
2018-09-23Unused PMP fields are WARL 0, not WIRIAndrew Waterman1-0/+1
2018-09-23unused mip fields are wpri instead of wiriAndrew Waterman1-0/+1
2018-09-23unused misa fields are wlrl, not wiriAndrew Waterman1-0/+1
2018-08-09Added specification that xRET instructions may, but are notKrste Asanovic1-1/+3
2018-04-13Add preface entryAndrew Waterman1-0/+1
2018-04-03Specify coarser-than-4-byte PMP semanticsAndrew Waterman1-0/+1
2018-03-21John Hauser's alternative writable-misa.C proposalAndrew Waterman1-0/+2
2017-12-12Describe optional support for misaligned AMOs (#117)Andrew Waterman1-0/+3
2017-12-11Fix xIE descriptive errorAndrew Waterman1-0/+2
2017-12-06Constrain all harts to use same A/D-bit management schemeAndrew Waterman1-0/+1
2017-11-09Make MPP/SPP WARL fieldsAndrew Waterman1-0/+1
2017-11-09Add hypervisor draft proposalAndrew Waterman1-0/+1
2017-11-09fix typosAndrew Waterman1-2/+2
2017-06-05Add preface entryAndrew Waterman1-1/+2
2017-06-03Add preface entry for SUM changeAndrew Waterman1-0/+2
2017-06-03Incorporate Allen's feedbackAndrew Waterman1-0/+13
2017-05-16Fix typo in change logMegan Wachs1-1/+1
2017-05-07user spec -> 2.2; priv spec -> 1.10Andrew Waterman1-1/+1
2017-05-07Remove SBI chapterAndrew Waterman1-0/+2
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