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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-21 14:21:15 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-21 14:21:15 -0700 |
| commit | ec7c8a047de4716adc61428edf4837f3eb02a95e (patch) | |
| tree | 2848d0c9d9e77ec36ee0c132b11ac2a8766ee97b /src/priv-preface.tex | |
| parent | 57fbcf9a3c3c68b83c900b75fce3a8acb7dfef08 (diff) | |
| download | riscv-isa-manual-ec7c8a047de4716adc61428edf4837f3eb02a95e.zip riscv-isa-manual-ec7c8a047de4716adc61428edf4837f3eb02a95e.tar.gz riscv-isa-manual-ec7c8a047de4716adc61428edf4837f3eb02a95e.tar.bz2 | |
Fix preface style
Diffstat (limited to 'src/priv-preface.tex')
| -rw-r--r-- | src/priv-preface.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 660a412..709f390 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -31,8 +31,8 @@ Changes from version 1.11 include: \itemsep 1pt \item Defined the RV32-only CSR {\tt mstatush}, which contains most of the same fields as the upper 32 bits of RV64's {\tt mstatus}. -\item A revised hypervisor architecture proposal that represents VS-mode - CSR state more simply. +\item Revised the hypervisor architecture proposal to represent VS-mode CSR + state more simply. \item Added optional big-endian and bi-endian support. \end{itemize} |