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| author | Stef O'Rear <sorear2@gmail.com> | 2020-07-22 07:40:54 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-22 04:40:54 -0700 |
| commit | a7b31e6eed2cd9fa06d2da5d0c4575cd3e3cc4c4 (patch) | |
| tree | 0b0ab4a8ee560eadccb683de3d0cde5a2ed4a950 /src/priv-preface.tex | |
| parent | 5736b2d3be39b9ae71f5801e1143d87628929c4d (diff) | |
| download | riscv-isa-manual-a7b31e6eed2cd9fa06d2da5d0c4575cd3e3cc4c4.zip riscv-isa-manual-a7b31e6eed2cd9fa06d2da5d0c4575cd3e3cc4c4.tar.gz riscv-isa-manual-a7b31e6eed2cd9fa06d2da5d0c4575cd3e3cc4c4.tar.bz2 | |
Pmp wording fix (#545)
* Consistently use "access-fault exception" for PMPs
Except for discussions of the xcause code itself which are "access
fault".
* Clarify behavior of locked TOR PMPs
Diffstat (limited to 'src/priv-preface.tex')
| -rw-r--r-- | src/priv-preface.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 879a787..3afa0a4 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -167,7 +167,7 @@ architecture proposal. Changes from version 1.9.1 include: without U-mode trap support, the {\tt medeleg} and {\tt mideleg} registers now do not exist, whereas previously they returned zero. \item Virtual-memory page faults now have {\tt mcause} values distinct from - physical-memory access exceptions. Page-fault exceptions can now be + physical-memory access faults. Page-fault exceptions can now be delegated to S-mode without delegating exceptions generated by PMA and PMP checks. \item An optional physical-memory protection (PMP) scheme has been proposed. |