diff options
| author | Andrew Waterman <andrew@sifive.com> | 2019-09-28 02:55:08 +0200 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-09-28 02:55:08 +0200 |
| commit | 4c730e36e2232e3aa7707c744d7b30360985159e (patch) | |
| tree | 42b38cd948765b8fa438d29a7592fab160978df0 /src/priv-preface.tex | |
| parent | 69a9f43a01b6a046b04bcb4a30d3cf8f9203c5a7 (diff) | |
| download | riscv-isa-manual-4c730e36e2232e3aa7707c744d7b30360985159e.zip riscv-isa-manual-4c730e36e2232e3aa7707c744d7b30360985159e.tar.gz riscv-isa-manual-4c730e36e2232e3aa7707c744d7b30360985159e.tar.bz2 | |
Update preface
Diffstat (limited to 'src/priv-preface.tex')
| -rw-r--r-- | src/priv-preface.tex | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index ebfb986..00499d1 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -37,6 +37,7 @@ Changes from version 1.11 include: annotations did not apply. \item Revised the hypervisor architecture proposal to represent VS-mode CSR state more simply. +\item Permitted the unconditional delegation of less-privileged interrupts. \item Stated that the {\tt scause} Exception Code field must implement bits 4--0 at minimum. \item Added optional big-endian and bi-endian support. |