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2024-07-30debug: update lds to merge more section (#573)Mark Zhuang2-6/+12
merge .bss.* to .bss then entry.S can clear it.
2024-06-27Change DTM IDCODE from SiFive HiFive1's 0x10e31913 to Spike's 0xdeadbeef (#565)Tommy Murphy4-5/+5
2024-05-01[debug tests] increase remotetimeout for all spike-based targets (#553)Anatoly Parshintsev8-10/+8
Spike simulator is very demanding to CPU resources. This causes debug tests to sporadically fail on slower machines. Increasing of gdb's `remotetimeout` should get rid of such failures, unless we run the testsuite on a potato. The only downside is that if OpenOCD is broken, tests can run longer. However, I think this is the sacrifice we can make, since execution time is not affected if everything works as expected.
2023-07-17debug: Add support_unavailable_control property.Tim Newsome7-0/+7
2023-05-01Update OpenOCD cfg files to new syntaxTim Newsome7-34/+34
We were using a variety of deprecated commands. The driving force behind this was the new way to use `expr{}` as the old way no longer works with mainline OpenOCD.
2022-10-24Increase timeouts for multi-spike test. (#423)Tim Newsome1-2/+1
Between October 13 and October 19, something happened that makes the multi-spike tests 4 times slower. Rolling back spike, OpenOCD, or riscv-tests doesn't affect this. Presumably it's due to a kernel or python change in my Ubuntu system. I don't have time to look at this right now, so just increase the timeouts. :-( If I had to guess, there could be a bug in rbb_daisychain.py that wastes a lot of time.
2022-10-21Change memory address used in debug tests. (#422)Tim Newsome2-2/+2
https://github.com/riscv-software-src/riscv-isa-sim/pull/889 put a UART at the address we were using in our 32-bit debug tests.
2022-10-12Get coverage of progbuf FPR accesses.Tim Newsome2-2/+4
Using the new spike support merged in https://github.com/riscv-software-src/riscv-isa-sim/pull/1109
2022-05-31Address pylint warnings. (#385)Tim Newsome6-13/+13
I'm running a newer version of pylint, and thus there are new warnings to be fixed. All very minor.
2022-05-16V implies FD now. (#382)Tim Newsome1-3/+3
Adjust test to work with that.
2021-11-12Set `riscv resume_order reversed`. (#363)Tim Newsome1-0/+2
The tests don't confirm that the order actually changes, but at least the code that does the work now is executed during the tests.
2021-10-05Remove slen. (#360)Tim Newsome3-18/+14
It's not an argument to spike anymore. Also switch testing the vector unit from multi-gdb to `-rtos hwthread`. This exposes a bug in OpenOCD (which is already fixed).
2021-05-20Test multiple heterogeneous spike instances. (#338)Tim Newsome3-22/+9
2021-05-07Test daisy chained homogeneous spike instances. (#334)Tim Newsome4-2/+89
* Test debugging multiple spikes in a daisy chain. * Hugely speed up rbb_daisychain. Now 2 dual-hart spikes are less than 4x slower than a single dual-hart spike. * WIP * Test daisy chained homogeneous spike instances. For OpenOCD, this means we're checking that we can talk to multiple TAPs. Next up is heterogeneous testing. * Enable Sv48Test. Didn't mean to disable it with this commit. * Test authentication again. Another change I hadn't meant to push...
2021-04-13Add FreeRTOS smoke tests. (#333)Tim Newsome3-4/+9
* Add FreeRTOS smoke tests. Make sure that OpenOCD can access all threads in a FreeRTOS binary on single-hart RV32 and RV64. * Also test `-rtos FreeRTOS`.
2021-01-25Smoketest that vl and vtype can be modified. (#320)Tim Newsome1-29/+0
2021-01-07Stop testing `-rtos riscv`. (#314)Tim Newsome1-20/+0
As of tomorrow that feature is officially no longer supported in OpenOCD, so stop testing it.
2020-12-31Make HiFiveUnleashed tests clean.Tim Newsome5-0/+9
HiFiveUnleashed-flash fails som address translation tests. Possibly that would be fixed when https://github.com/riscv/riscv-tests/pull/313 merges.
2020-12-14Add tests for memory sampling feature. (#300)Tim Newsome6-0/+6
2020-10-08Expose registers on all harts in openocd cfgs (#297)Samuel Obuch2-4/+10
2020-08-06Add enable_rtos_riscv (#288)Tim Newsome1-0/+2
This is now required to use `-rtos riscv`. Addresses the aside mentioned in #287.
2020-06-25Add manual hwbp test. (#283)Tim Newsome2-0/+2
Make sure OpenOCD cooperates when a user sets a trigger by writing tselect/tdata* directly.
2020-05-26Test semihosting calls (#280)Tim Newsome5-5/+14
* Add a basic semihosting test. * Need to configure semihosting on each target. * WIP * Parse "cannot insert breakpoint" message. Also use sys.exit instead of exit, per new pylint's suggestion.
2020-04-10Change slen to a value that spike supports. (#271)Tim Newsome1-1/+3
2020-03-18Specify misa for HiFive Unleashed. (#259)Tim Newsome1-0/+2
This saves a few seconds every time I run any test.
2020-02-14Add tests for vector register access (#244)Tim Newsome3-10/+13
* WIP * Add vector register smoketest. Also redo the gdb value parsing code to accommodate the more complicated way that vector registers look. * Test vector access a little more thoroughly. * Revert unnecessary changes.
2019-12-18Hardcode misa values for all spike targets. (#227)Tim Newsome8-7/+19
`make` now takes 31s, `make all` takes 1m53s. The new CheckMisa test ensures that the misa value specified in the configuration is correct.
2019-12-02Use a small binary to set up HiFive Unleashed. (#221)Tim Newsome3-10/+10
This binary comes from https://github.com/timsifive/freedom-u540-c000-bootloader/tree/board_setup2, which will hopefully be accepted upstream.
2019-10-15Add support to run all tests against HiFive Unleashed. (#212)Tim Newsome5-0/+184
* Parse inf/nan floats. * Enable mstatus.fs in SimpleF18Test Also accept "unable to fetch" message when FPRs aren't supported. * Add config files for HiFive Unleashed. * Add configs to flash HiFive Unleashed. All tests pass.
2019-10-09Remove ocd_ prefix. (#210)Tim Newsome4-4/+4
The latest OpenOCD doesn't need (nor support) this anymore.
2019-08-02Miscellaneous minor test improvements (#199)Tim Newsome1-1/+3
* Let the debugger enable mstatus.F if necessary. * Ignore (some) gdb debug output. * Increase timeout. * Make newer version of pylint happy.
2019-07-15Use work area in spike-1 to cover CRC algorithm. (#195)Tim Newsome1-0/+2
2019-05-16Cover with/without halt groups. (#191)Tim Newsome4-5/+6
Also work with the new command line options that were renamed in https://github.com/riscv/riscv-isa-sim/pull/299
2019-04-08Test lack of abstract CSR access. (#187)Tim Newsome6-6/+9
2019-04-04Test simultaneous resume using hasel. (#186)Tim Newsome4-5/+11
Passes on spike and Arty. Won't merge until https://github.com/riscv/riscv-openocd/pull/364 merges.
2019-02-14Test `-rtos hwthread` (#178)Tim Newsome3-0/+57
* WIP * Use hwthread everywhere. * Test `-rtos hwthread`. Also tweak timeouts a bit so that we don't have ridiculous timeouts for simple operations. * Tweak timeouts so tests pass on a loaded system.
2018-12-31Add testing of run-test/idle cases.Tim Newsome6-6/+7
2018-11-14Merge pull request #165 from riscv/flashTim Newsome2-0/+59
Tweak debug tests to run out of flash.
2018-11-14Cleanup and renamed test flag to invalid_memory_returns_zerocgsfv2-2/+2
2018-11-13Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fixcgsfv2-2/+4
2018-10-31Add HiFive1-flash target configuration.Tim Newsome2-0/+59
2018-09-13Assert if HiFive1 program is too large.Tim Newsome1-0/+2
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome9-0/+9
Only works against spike, where I've implemented some custom debug registers to test against.
2018-04-19Delete E300Sim.pydebug-delete-simMegan Wachs1-17/+0
This file is wrong (the .cfg file isn't right) and not used by anything.
2018-04-02Use `gdb_report_register_access_error enable`Tim Newsome4-0/+6
2018-03-27Test debug authentication.Tim Newsome3-3/+18
Also halt instead of reset spike targets, which tests a more complicated code path.
2018-03-01Test debugging with/without a program bufferTim Newsome3-3/+3
2018-03-01Ensure an error when reading a non-existent CSR.Tim Newsome4-0/+16
2018-02-07Link scripts shouldn't be executable.Tim Newsome1-0/+0
2017-12-27Test FPRs that aren't XLEN in size.Tim Newsome4-4/+6
Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
generated by cgit v1.1 at 2024-08-16 03:24:09 +0000