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| author | Tim Newsome <tim@sifive.com> | 2020-05-26 12:37:09 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-26 12:37:09 -0700 |
| commit | fbe74f48e16be28a2b360e8a9e845b01d9e4b167 (patch) | |
| tree | 869b79d740a4c5f405f35eb0cab9275ea7da47e0 /debug/targets | |
| parent | bc4c1d2866b896f6234d19111993fae4a9f47d74 (diff) | |
| download | riscv-tests-fbe74f48e16be28a2b360e8a9e845b01d9e4b167.zip riscv-tests-fbe74f48e16be28a2b360e8a9e845b01d9e4b167.tar.gz riscv-tests-fbe74f48e16be28a2b360e8a9e845b01d9e4b167.tar.bz2 | |
Test semihosting calls (#280)
* Add a basic semihosting test.
* Need to configure semihosting on each target.
* WIP
* Parse "cannot insert breakpoint" message.
Also use sys.exit instead of exit, per new pylint's suggestion.
Diffstat (limited to 'debug/targets')
| -rw-r--r-- | debug/targets/RISC-V/spike-1.cfg | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike-2-hwthread.cfg | 6 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike-2.cfg | 9 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32-2-rtos.py | 1 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64-2-rtos.py | 1 |
5 files changed, 14 insertions, 5 deletions
diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg index d1ed60e..3bc32d1 100644 --- a/debug/targets/RISC-V/spike-1.cfg +++ b/debug/targets/RISC-V/spike-1.cfg @@ -26,3 +26,5 @@ set challenge [riscv authdata_read] riscv authdata_write [expr $challenge + 1] halt + +arm semihosting enable diff --git a/debug/targets/RISC-V/spike-2-hwthread.cfg b/debug/targets/RISC-V/spike-2-hwthread.cfg index 31a5f68..94bac00 100644 --- a/debug/targets/RISC-V/spike-2-hwthread.cfg +++ b/debug/targets/RISC-V/spike-2-hwthread.cfg @@ -11,7 +11,6 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 set _TARGETNAME_0 $_CHIPNAME.cpu0 set _TARGETNAME_1 $_CHIPNAME.cpu1 target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -rtos hwthread -#target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 -rtos hwthread target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 target smp $_TARGETNAME_0 $_TARGETNAME_1 @@ -29,3 +28,8 @@ set challenge [riscv authdata_read] riscv authdata_write [expr $challenge + 1] halt + +foreach t [target names] { + targets $t + arm semihosting enable +} diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg index c9de7d2..0eadb89 100644 --- a/debug/targets/RISC-V/spike-2.cfg +++ b/debug/targets/RISC-V/spike-2.cfg @@ -26,7 +26,8 @@ init set challenge [riscv authdata_read] riscv authdata_write [expr $challenge + 1] -targets $_TARGETNAME_0 -halt -targets $_TARGETNAME_1 -halt +foreach t [target names] { + targets $t + halt + arm semihosting enable +} diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py index 8872739..e221353 100644 --- a/debug/targets/RISC-V/spike32-2-rtos.py +++ b/debug/targets/RISC-V/spike32-2-rtos.py @@ -10,6 +10,7 @@ class spike32_2(targets.Target): timeout_sec = 30 implements_custom_test = True support_hasel = False + test_semihosting = False def create(self): return testlib.Spike(self, progbufsize=0, dmi_rti=4, diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py index db6263a..3b9c1d8 100644 --- a/debug/targets/RISC-V/spike64-2-rtos.py +++ b/debug/targets/RISC-V/spike64-2-rtos.py @@ -10,6 +10,7 @@ class spike64_2_rtos(targets.Target): timeout_sec = 60 implements_custom_test = True support_hasel = False + test_semihosting = False def create(self): return testlib.Spike(self, abstract_rti=30, support_hasel=False, |