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| author | Tim Newsome <tim@sifive.com> | 2020-12-14 12:40:54 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-14 12:40:54 -0800 |
| commit | 67cb46859f51e71d4fc17df22673d7410056fbb7 (patch) | |
| tree | 5e001d039f4df8af633e4f4481d443e0cab7001e /debug/targets | |
| parent | cbeadfda33ba8bc04b620a49bda8873fd52b9f1c (diff) | |
| download | riscv-tests-67cb46859f51e71d4fc17df22673d7410056fbb7.zip riscv-tests-67cb46859f51e71d4fc17df22673d7410056fbb7.tar.gz riscv-tests-67cb46859f51e71d4fc17df22673d7410056fbb7.tar.bz2 | |
Add tests for memory sampling feature. (#300)
Diffstat (limited to 'debug/targets')
| -rw-r--r-- | debug/targets/RISC-V/spike32-2-hwthread.py | 1 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32-2-rtos.py | 1 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32.py | 1 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64-2-hwthread.py | 1 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64-2-rtos.py | 1 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64-2.py | 1 |
6 files changed, 6 insertions, 0 deletions
diff --git a/debug/targets/RISC-V/spike32-2-hwthread.py b/debug/targets/RISC-V/spike32-2-hwthread.py index 2ad2998..e84391a 100644 --- a/debug/targets/RISC-V/spike32-2-hwthread.py +++ b/debug/targets/RISC-V/spike32-2-hwthread.py @@ -9,6 +9,7 @@ class spike32_2(targets.Target): openocd_config_path = "spike-2-hwthread.cfg" timeout_sec = 5 implements_custom_test = True + support_memory_sampling = False # not supported without sba def create(self): return testlib.Spike(self, isa="RV32IMAV", support_hasel=True, diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py index ce0d56d..81029e8 100644 --- a/debug/targets/RISC-V/spike32-2-rtos.py +++ b/debug/targets/RISC-V/spike32-2-rtos.py @@ -12,6 +12,7 @@ class spike32_2(targets.Target): support_hasel = False test_semihosting = False support_manual_hwbp = False # not supported with `-rtos riscv` + support_memory_sampling = False # not supported with `-rtos riscv` def create(self): return testlib.Spike(self, progbufsize=0, dmi_rti=4, diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index b261f6c..913dccf 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -17,6 +17,7 @@ class spike32(targets.Target): openocd_config_path = "spike-1.cfg" timeout_sec = 30 implements_custom_test = True + support_memory_sampling = False # Needs SBA def create(self): # 64-bit FPRs on 32-bit target diff --git a/debug/targets/RISC-V/spike64-2-hwthread.py b/debug/targets/RISC-V/spike64-2-hwthread.py index 5d8d6e6..ee1a46b 100644 --- a/debug/targets/RISC-V/spike64-2-hwthread.py +++ b/debug/targets/RISC-V/spike64-2-hwthread.py @@ -9,6 +9,7 @@ class spike64_2(targets.Target): openocd_config_path = "spike-2-hwthread.cfg" timeout_sec = 5 implements_custom_test = True + support_memory_sampling = False # Needs SBA def create(self): return testlib.Spike(self) diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py index 2062f6d..acb217f 100644 --- a/debug/targets/RISC-V/spike64-2-rtos.py +++ b/debug/targets/RISC-V/spike64-2-rtos.py @@ -12,6 +12,7 @@ class spike64_2_rtos(targets.Target): support_hasel = False test_semihosting = False support_manual_hwbp = False # not supported with `-rtos riscv` + support_memory_sampling = False # not supported with `-rtos riscv` def create(self): return testlib.Spike(self, abstract_rti=30, support_hasel=False, diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py index 5dc0e7b..ceb2227 100644 --- a/debug/targets/RISC-V/spike64-2.py +++ b/debug/targets/RISC-V/spike64-2.py @@ -12,6 +12,7 @@ class spike64_2(targets.Target): timeout_sec = 20 implements_custom_test = True support_hasel = False + support_memory_sampling = False # Needs SBA def create(self): # TODO: It would be nice to test with slen=128, but spike currently |