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| author | Tim Newsome <tim@sifive.com> | 2021-01-25 11:26:51 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-01-25 11:26:51 -0800 |
| commit | e75931826097c741f274212a49302e39ca597168 (patch) | |
| tree | 08c9997cb28e08fa7c35a63f8cce689ad18a015a /debug/targets | |
| parent | e35ee2822f3ffa3c24e7c857c3688f8f260cd98c (diff) | |
| download | riscv-tests-e75931826097c741f274212a49302e39ca597168.zip riscv-tests-e75931826097c741f274212a49302e39ca597168.tar.gz riscv-tests-e75931826097c741f274212a49302e39ca597168.tar.bz2 | |
Smoketest that vl and vtype can be modified. (#320)
Diffstat (limited to 'debug/targets')
| -rw-r--r-- | debug/targets/RISC-V/spike-rtos.cfg | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg deleted file mode 100644 index 395a9f8..0000000 --- a/debug/targets/RISC-V/spike-rtos.cfg +++ /dev/null @@ -1,29 +0,0 @@ -# Connect to a mult-icore RISC-V target, exposing each hart as a thread. -adapter_khz 10000 - -interface remote_bitbang -remote_bitbang_host $::env(REMOTE_BITBANG_HOST) -remote_bitbang_port $::env(REMOTE_BITBANG_PORT) - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 - -enable_rtos_riscv - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv - -gdb_report_data_abort enable -gdb_report_register_access_error enable - -# Expose an unimplemented CSR so we can test non-existent register access -# behavior. -riscv expose_csrs 2288 -riscv expose_custom 1,12345-12348 - -init - -set challenge [riscv authdata_read] -riscv authdata_write [expr $challenge + 1] - -halt |