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2023-10-27Merge commit '9f23a1d7c1e27c556ef9787b9d3f263f5c1ecf24' into from_upstreamTim Newsome12-37/+456
Conflicts: HACKING src/target/riscv/riscv-013.c Change-Id: I43ccb143cae8daa39212d66a8824ae3ad2af6fef
2023-10-23Merge commit 'e17fe4db0f256ee4fb97dcfd6b9f7f55c966b190' into from_upstreamTim Newsome1-8/+13
Conflicts: src/flash/nor/drivers.c src/target/riscv/riscv.c Change-Id: Ide3eded7e0d5b0b446bfd0873a32c00cc9f128bd
2023-10-16Merge commit '0384fe5d596f42388f8b84d42959d899f29388ab' into from_upstreamTim Newsome1-4/+20
Conflicts: .github/workflows/snapshot.yml src/rtos/FreeRTOS.c Change-Id: I4c9ff887b69140e0f61cb3f75a2f2c1a12071320
2023-10-07target/nrf52: Create and configure TPIUFrank Plowman1-0/+49
Firstly, create the TPIU nrf52.tpiu if using the nrf52 target. This is standard, using AP 0 and TPIU base address 0xE0040000. Secondly, add a pre_enable handler for this TPIU which configures the TRACEMUX field of the TRACECONFIG register. This register is reset every time the MCU resets, so the pre_enable handler creates a reset-end handler to ensure the register remains set. Change-Id: I408b20fc03dc2060c21bad0c21ed713eee55a113 Signed-off-by: Frank Plowman <post@frankplowman.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7901 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-10-07tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map accessNishanth Menon1-0/+3
While we can read and write from memory from the view of various processors, all K3 debug systems have a AXI Access port that allows us to directly access memory from debug interface. This port is especially useful in the following scenarios: 1. Debug cache related behavior on processors as this provides a direct bypass path. 2. Processor has crashed or inaccessible for some reason (low power state etc.) 3. Scenarios prior to the processor getting active. 4. Debug MMU or address translation issues (example: TI's Region Address Table {RAT} translation table used to physically map SoC address space into R5/M4F processor address space) The AXI-AP port is the same for all processors in TI's K3 family. To prevent a circular-loop scenario for axi-ap accessing debug memory with dmem (direct memory access debug), enable this only when dmem is disabled. Change-Id: Ie4ca9222f034ffc2fa669fb5124a5f8e37b65e3b Reported-by: Dubravko Srsan <dubravko.srsan@dolotron.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7899 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-10-07tcl/target/ti_k3: Introduce RTOS array variable to set various CPU RTOSesNishanth Menon1-4/+17
The Texas Instruments' K3 devices are a mix of AMP and SMP systems. The operating systems used on these processors can vary dramatically as well. Introduce a RTOS array variable, which is keyed off the cpu to identify which RTOS is used on that CPU. This can be "auto" or "hwthread" in case of SMP debug etc. For example: AM625 with an general purpose M4F running Zephyr and 4 A53s running SMP Linux could be invoked by: openocd -c 'set V8_SMP_DEBUG 1' -c 'set RTOS(am625.cpu.gp_mcu) Zephyr' \ -c "set RTOS(am625.cpu.a53.0) hwthread" -f board/ti_am625evm.cfg Change-Id: Ib5e59fa2583b3115e5799658afcdd0ee91935e82 Reported-by: Dubravko Srsan <dubravko.srsan@dolotron.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7898 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-07tcl/target/ti_k3: Add coreid identification to SMP processorsDubravko Srsan1-1/+1
Describe the SMP Armv8 cores in SMP configuration with coreid explicitly called out. This allows for gdb session to call the smp behavior clearly. Change-Id: Ie43be22db64737bbb66181f09d3c83567044f3ac Signed-off-by: Dubravko Srsan <dubravko.srsan@dolotron.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7897 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-10-07tcl/target/ti_k3: Fix smp target descriptionDubravko Srsan1-1/+1
When _v8_smp_targets is used with V8_SMP_DEBUG=1, describe the targets as SMP targets. However, the variable expansion is not in the context of a proc, and a typo in referring to global $_v8_smp_targets causes this to fail. Just refer to $_v8_smp_targets directly. Change-Id: Iffe5fd2703bed6a9c840284285e70b8a8ce84e17 Signed-off-by: Dubravko Srsan <dubravko.srsan@dolotron.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7896 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-09-23tcl/target: add support for Cavium Octeon II CN61xxPeter Mamonov1-0/+15
Change-Id: Ia14854bc64f5a31b6591be69be4edee9cd1310c3 Signed-off-by: Peter Mamonov <pmamonov@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/5249 Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-09-23tcl/target: Add XLP3xx configuration filesPeter Mamonov4-0/+60
The patch adds configuration files for the following XLP 300-series processors: XLP304, XLP308, XLP316. Change-Id: Iaf2b807abf9fc4d7b51222fd40bdb18c6aca7d9c Signed-off-by: Aleksey Kuleshov <rndfax@yandex.ru> Signed-off-by: Peter Mamonov <pmamonov@gmail.com> CC: Antony Pavlov <antonynpavlov@gmail.com> CC: Dongxue Zhang <elta.era@gmail.com> CC: Oleksij Rempel <linux@rempel-privat.de> CC: Paul Fertser <fercerpav@gmail.com> CC: Salvador Arroyo <sarroyofdez@yahoo.es> CC: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: https://review.openocd.org/c/openocd/+/2323 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-09-23tcl/target/ti_k3: Add AM62P SoCNishanth Menon1-2/+11
Add support for the TI K3 family AM62P SoC. This SoC is built on the same base of AM62A7, so reuse the configuration with the exception of the JTAG ID and the actual name used for the R5 core (moved from main domain to wakeup domain). For further details, see https://www.ti.com/lit/pdf/spruj83 Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I3a80be9e71204ed7697e51ac1ad488ef405744ef Reviewed-on: https://review.openocd.org/c/openocd/+/7892 Reviewed-by: Bryan Brattlof <hello@bryanbrattlof.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-09-23tcl/target/ti_k3: Add J784s4 SoCNishanth Menon1-0/+33
Add support for the TI K3 family J784S4/AM69 SoC. For further details, see http://www.ti.com/lit/zip/spruj52 Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I3c899aed0cb79ab8bbf8077ca6dfe0636cf72288 Reviewed-on: https://review.openocd.org/c/openocd/+/7890 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-09-23tcl/target/ti_k3: Set _CHIPNAME in one placeNishanth Menon1-7/+2
$_soc is set per platform, no point in duplicating _CHIPNAME to explicitly set the information provided by $_CHIPNAME itself. So move it out after the check for CHIP_NAME Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I60d30d6a9a2ce352f66c5bc03075e4ba638e3062 Reviewed-on: https://review.openocd.org/c/openocd/+/7889 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-09-19flash/stm32l4x: support STM32WBA5xx devicesTarek BOCHKATI1-0/+106
STM32WBA5x have a single bank flash up to 1MB Change-Id: I3d720e202f0fdd89ecd8aa7224653ca5a7ae187b Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com> Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7694 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-09-12Merge commit 'ee31f1578a333a75737bc5b183cd4ae98cdaf798' into from_upstreamTim Newsome1-0/+30
Conflicts: Makefile.am jimtcl src/helper/Makefile.am src/rtos/rtos.c src/rtos/rtos.h src/rtos/rtos_standard_stackings.c Change-Id: I00c98d20089558744988184370a8cb7f95f03329
2023-09-08flash/nor: add support for Nuvoton NPCX4/K3 series flashLuca Hung1-2/+8
Added NPCX flash driver to support the Nuvoton NPCX4/K3 series microcontrollers. Add config file for these series. Change-Id: I0b6e128fa51146b561f422e23a98260594b1f138 Signed-off-by: Luca Hung <YCHUNG0@nuvoton.com> Signed-off-by: Mulin CHao <mlchao@nuvoton.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7794 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-08-29Merge commit 'dfbbfac4d72e247e8094a49c8573b2f49689b6d5' into from_upstreamTim Newsome1-1/+9
Change-Id: I6e7c0866291dd87946a4fd49d9bfe4cddefb3957
2023-08-26tcl/board: Add j721e native swd configurationKaelin Laundry1-0/+10
Direct memory driver swd native configuration for j721E Signed-off-by: Kaelin Laundry <wasabifan@outlook.com> Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I27455040f48c47271ae110afd114fce005824969 Reviewed-on: https://review.openocd.org/c/openocd/+/7259 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-08-26tcl/board: Add am625 native swd configurationNishanth Menon1-0/+29
Direct memory driver swd native configuration for am625. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Jason Peck <jpeck@ti.com> Change-Id: I6cf521fe9af0a4b8f8ab4853bc25722368b713e6 Reviewed-on: https://review.openocd.org/c/openocd/+/7091 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-08-26tcl/target/ti_k3: Add AM62A7 SoCJason Kacines1-0/+23
Add support for the TI K3 family AM62A7 SoC. For further details, see https://www.ti.com/lit/pdf/spruj16a Change-Id: Ie69bde4895f34b04f9967f63d1ca9c8149c50b8a Signed-off-by: Jason Kacines <j-kacines@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7854 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2023-08-26tcl/target/ti_k3: Add missing documentation for supported SoCsJason Kacines1-0/+4
Add links for the SoCs are supported by the conf file for future reference. Change-Id: Ic5b7786ef3ac31414fe2ce56c1237a18ce99aaa1 Signed-off-by: Jason Kacines <j-kacines@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7853 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-08-26tcl/target: add Realtek RTL872xD configKarl Palsson1-0/+33
Sufficient to probe both cores via multiple APs. No support listed for jtag in the datasheet or usermanual. Tested against a BW-16 board: https://www.amebaiot.com/en/amebad/#partner_bw16 Change-Id: Idf82085e7b7327fdf3d6d668e6fb59eff6e0431b Signed-off-by: Karl Palsson <karlp@tweak.au> Reviewed-on: https://review.openocd.org/c/openocd/+/7847 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-08-12tcl: add configuration files for the ARC HSDK-4xD boardArtemiy Volkov1-0/+50
This commit provides startup files for the Synopsys DesignWare ARC HSDK-4xD board. These have been adapted from the corresponding snps_hsdk.cfg files, the only functional change being the JTAG IDs for the new board's CPU cores. Change-Id: I19a0cd13bc09de90cfe2a7cccf1239e459fd8077 Signed-off-by: Artemiy Volkov <artemiy@synopsys.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7829 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Evgeniy Didin <didin@synopsys.com>
2023-07-31Merge pull request #884 from riscv/from_upstreamTim Newsome5-8/+66
Merge up to a3ed12401 from upstream.
2023-07-19tcl/target: add Espressif riscv targets (ESP32-C6, ESP32-H2)Erhan Kurubas2-0/+264
ESP32-C6 and ESP32-H2 are single core riscv targets. Change-Id: If92429de4fb67a040f303a54177d61b70e1ea281 Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-19tcl/target: update esp32c2.cfg to reference shared functions in the ↵Erhan Kurubas1-62/+68
esp_common.cfg This commit enhances code reusability, simplifies maintenance, and ensures consistency across all chip configurations by consolidating commonly used commands and variables into the common config file. Change-Id: I825dd4fddb88e5514429d49ab13869ee6b9a28fc Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-19tcl/target: update esp32c3.cfg to reference shared functions in the ↵Erhan Kurubas2-65/+52
esp_common.cfg This commit enhances code reusability, simplifies maintenance, and ensures consistency across all chip configurations by consolidating commonly used commands and variables into the common config file. Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: Ie3413d3149388b17bc0199409ce86d3eb7cf5ee2
2023-07-19tcl/target: update esp32s3.cfg to reference shared functions in the ↵Erhan Kurubas1-92/+12
esp_common.cfg This commit enhances code reusability, simplifies maintenance, and ensures consistency across all chip configurations by consolidating commonly used commands and variables into the common config file. Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: Ifb0122f3b98a767f27746409499733b70fb7d0e8 Reviewed-on: https://review.openocd.org/c/openocd/+/7747 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-19tcl/target: update esp32s2.cfg to reference shared functions in the ↵Erhan Kurubas1-50/+12
esp_common.cfg This commit enhances code reusability, simplifies maintenance, and ensures consistency across all chip configurations by consolidating commonly used commands and variables into the common config file. Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: I36c86fe4ebc99928ce48a5bff8cb9580a0fa3ac0 Reviewed-on: https://review.openocd.org/c/openocd/+/7746 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-19tcl/target: update esp32.cfg to reference shared functions in the esp_common.cfgErhan Kurubas1-79/+15
This commit enhances code reusability, simplifies maintenance, and ensures consistency across all chip configurations by consolidating commonly used commands and variables into the common config file. Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: I9181737d83eeba4e983b6a455b8a1523f2576dd2 Reviewed-on: https://review.openocd.org/c/openocd/+/7745 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-07-19tcl/target: move Espressif shared functions to esp_common.cfgErhan Kurubas1-5/+178
Consolidate commonly used commands and variables from chip config files into functions in esp_common.cfg. This includes "jtag newtap," "target create,"and "configure -event." Enhances code reusability and simplifies maintenance. Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: I9e8bf07a4a15d4544ceb564607dea66837381d70 Reviewed-on: https://review.openocd.org/c/openocd/+/7744 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-14tcl/target: update esp32s3.cfg to reference shared functions in the ↵Erhan Kurubas1-92/+12
esp_common.cfg This commit enhances code reusability, simplifies maintenance, and ensures consistency across all chip configurations by consolidating commonly used commands and variables into the common config file. Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: Ifb0122f3b98a767f27746409499733b70fb7d0e8 Reviewed-on: https://review.openocd.org/c/openocd/+/7747 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-14tcl/target: update esp32s2.cfg to reference shared functions in the ↵Erhan Kurubas1-50/+12
esp_common.cfg This commit enhances code reusability, simplifies maintenance, and ensures consistency across all chip configurations by consolidating commonly used commands and variables into the common config file. Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: I36c86fe4ebc99928ce48a5bff8cb9580a0fa3ac0 Reviewed-on: https://review.openocd.org/c/openocd/+/7746 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-14tcl/target: update esp32.cfg to reference shared functions in the esp_common.cfgErhan Kurubas1-79/+15
This commit enhances code reusability, simplifies maintenance, and ensures consistency across all chip configurations by consolidating commonly used commands and variables into the common config file. Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: I9181737d83eeba4e983b6a455b8a1523f2576dd2 Reviewed-on: https://review.openocd.org/c/openocd/+/7745 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-07-14tcl/target: move Espressif shared functions to esp_common.cfgErhan Kurubas1-3/+182
Consolidate commonly used commands and variables from chip config files into functions in esp_common.cfg. This includes "jtag newtap," "target create,"and "configure -event." Enhances code reusability and simplifies maintenance. Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: I9e8bf07a4a15d4544ceb564607dea66837381d70 Reviewed-on: https://review.openocd.org/c/openocd/+/7744 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-12Merge commit 'a3ed12401b1f7d9578fb7da881d3504e07acfc27' into from_upstreamTim Newsome5-8/+66
Conflicts: src/target/riscv/riscv-013.c src/target/riscv/riscv.c Change-Id: I65bdb4d28c91e9022ce811de976c9bf474a0b590
2023-07-08pld/virtex2: add program/refresh commandDaniel Anselmi1-0/+1
Change-Id: If6d237a6f27c4232849f73d08e7ca74276e6d464 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7714 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-07-08tcl/cpld: add config files for more xilinx fpga familiesDaniel Anselmi1-0/+1
Use configurable virtex pld driver to add support for more xilinx fpga families. Change-Id: Iff10c8c511787734fa289bdba15f03131d51e071 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7352 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-07-08pld: give devices a name for referencing in scriptsDaniel Anselmi1-1/+1
Change-Id: I05e8596ffacdb6cd8da4dd8a40bb460183f4930a Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7728 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-06-10target/ti-cjtag: make switching to JTAG more reliableLorenz Brun1-0/+1
The current cJTAG to JTAG switching commands for TI chips are not particularly reliable, especially on chips with accurate timing. On a Raspberry Pi the existing sequence has (depending on cabling and chip) a ~50% chance of working, on a much better-behaved FT2232H it doesn't manage to enable full JTAG at all. This change runs a bunch of test-idle cycles before actually attempting to switch to full JTAG. This makes the switch reliable even at high clock speeds (>100kHz) and from precise sources like the FT2232H. Change-Id: I9293e884bf3e9606d529756ae4483b844d3c39db Reported-by: Phil Wiggum <p1mail2015@mail.com> Fixes: https://sourceforge.net/p/openocd/tickets/375/ Signed-off-by: Lorenz Brun <lorenz@brun.one> Reviewed-on: https://review.openocd.org/c/openocd/+/7419 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-06-10flash/nor: add support for NXP QN908xiosabi1-0/+38
This patch adds support for the NXP QN908x family of Bluetooth microcontrollers, such as the QN9080. This chip features a Cortex-M4F with 512 KiB of flash on all the available versions, although the documentation suggests that there might be 256 kB versions as well. The initial support allows to read, erase and write the whole user flash area. Three new sub-commands under the new "qn908x" command are added in this patch as well: disable_wdog to disabled the watchdog, mass_erase to perform a mass erase and allow_brick to allow programming images that disable the SWD interface. Disabling the watchdog is required after a "reset halt" in order to run the CRC algorithm from RAM when verifying the chip. However, this is not done automatically on probing or other initialization since disabling the watchdog might interfere with debugging real applications. The "mass_erase" command allows to erase the whole flash without probing it, since in some scenarios the chip can be locked such that no flash or ram can be accessed from the SWD interface, allowing only to run a mass_erase to be able to flash the program. The flashing process allows to compute a checksum, similar to the lpc2000 driver "calc_checksum" but done over a different region of the memory. This checksum is required to be present for the QN908x bootloader ROM to boot, and otherwise is useless. As with the lpc2000 design, verification when using "calc_checksum" is expected to fail if the checksum was not valid in the image being verified. This was manually tested on a QN9080, including the scan-view, AddressSanitizer/UBSan and test coverage configurations. Change-Id: Ibd6d8f3608654294795085fcaaffb448b77cc58b Co-developed-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de> Signed-off-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de> Signed-off-by: iosabi <iosabi@protonmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/5584 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-06-02jtag/vdebug: adding xtensa configJacek Wuwer2-27/+166
This change adds the extensa sample target and board configurations. it removes the obsoleted vd_xtensa_jtag.cfg from targets. Change-Id: I9d4d25abde46c0b15e5211a973012447872cb405 Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7723 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-06-02Add/Correct STM8L15xx2/3/4/6/8 devicesDominik Wernberger6-1/+169
Change-Id: I83fe1e50821ec15e1853aca96ebb32fe1ff5328f Signed-off-by: Dominik Wernberger <dominik.wernberger@gmx.de> Reviewed-on: https://review.openocd.org/c/openocd/+/7690 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-05-24flash/stm32l4x: support STM32C0x devicesTarek BOCHKATI1-0/+74
this new STM32 series family introduces 2 devices: STM32C011xx (0x443) and STM32C031xx (0x453) both devices have 32 Kbytes single flash bank. Change-Id: I4e890789e44e3b174c0e9c0e1068383ecdbb865f Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6874 Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp> Tested-by: jenkins Reviewed-by: zapb <dev@zapb.de> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-05-18tcl/target: Add support for TMS570LC43xxPhil Kirkpatrick2-9/+9
Added support for TMS570LC43xx series parts. This uses the pre-existing ti_tms570.cfg parent config. In ti_tms570.cfg, dbgbase was changed. Note 1: Based on the following TI E2E post, the previous dbgbase was wrong and the new value isn't due to a difference in parts. Link: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1106954/tms570ls3137-debugging-with-openocd Note 2: Both the previous dbgbase and the one suggested in the TI E2E post have the 2 LSB set. In the current version of OpenOCD, this will cause cortex_a_read_cpu_memory_fast and cortex_a_write_cpu_memory_fast to fail due to an alignment checks in mem_ap_<read/write>_buf_noincr()->mem_ap_<read/write>(). In all other uses of dbgbase for arm cortex parts, the 2 LSB are masked and ignored. Change-Id: Ic936722e5a4cfc7161b0df1fe3325ee12fd901c6 Signed-off-by: Phil Kirkpatrick <p.kirkpatrick@reflexaerospace.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7682 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-05-04Merge commit '228fe7300c7df7aa05ba2c0bc19edde6d0156401' into from_upstreamTim Newsome14-245/+242
Conflicts: doc/openocd.texi src/jtag/aice/aice_pipe.c src/jtag/aice/aice_usb.c src/rtos/FreeRTOS.c src/rtos/hwthread.c src/rtos/rtos_standard_stackings.c src/target/riscv/riscv.c Change-Id: I0c6228c499d60274325be895fbcd8007ed1699bc
2023-04-30tcl/target: renesas gen3 Set target to armv8r for Cortex-R52Julien Massot1-8/+13
Cortex-R52 is an ARMv8-R processor supporting only AArch32 Profile. Signed-off-by: Julien Massot <julien.massot@iot.bzh> Change-Id: I663ae4bf1d3026d7c9e4c5950a79e7ddf1bd6564 Reviewed-on: https://review.openocd.org/c/openocd/+/6805 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-04-14tcl: zynq_7000: add missing id codesDaniel Anselmi1-4/+20
Add missing ID codes and ignore the version in the ID. Change-Id: Idd2d3a5eddb6995f3af1c45afd2adf76ce3442bf Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7386 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-03-16Merge commit '1293ddd65713d6551775b67169387622ada477c1' into from_upstreamTim Newsome287-40/+2497
This includes https://sourceforge.net/p/openocd/mailman/message/37710818/, which should fix #814. Conflicts: .travis.yml contrib/loaders/flash/stm32/stm32f1x.S contrib/loaders/flash/stm32/stm32f2x.S doc/openocd.texi src/rtos/FreeRTOS.c src/server/gdb_server.c src/target/riscv/riscv-013.c src/target/riscv/riscv.c src/target/riscv/riscv.h src/target/riscv/riscv_semihosting.c tcl/target/esp_common.cfg tcl/target/gd32vf103.cfg tools/scripts/checkpatch.pl Change-Id: I1986c13298ca0dafbe3aecaf1b0b35626525e4eb
2023-02-28Merge commit 'd1b882f2c014258be5397067e45848fa5465b78b' into from_upstreamTim Newsome7-63/+162
Conflicts: doc/openocd.texi src/target/riscv/riscv-013.c src/target/riscv/riscv.c Change-Id: I8cd557a10c3d5beeaed05ecc05d4c325a9ee7e70
generated by cgit v1.1 at 2024-10-06 17:31:25 +0000