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| author | Tim Newsome <tim@sifive.com> | 2023-08-29 13:10:44 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2023-08-29 13:10:44 -0700 |
| commit | 0801c66ff4cabfc44a7e89e8b798299c391a1d4c (patch) | |
| tree | 6924503592793955ae5802319a4a5e96ea937b75 /tcl/target | |
| parent | 5efea16944ceb7b0797755f21ee131dc8b3d90c2 (diff) | |
| parent | dfbbfac4d72e247e8094a49c8573b2f49689b6d5 (diff) | |
| download | riscv-openocd-0801c66ff4cabfc44a7e89e8b798299c391a1d4c.zip riscv-openocd-0801c66ff4cabfc44a7e89e8b798299c391a1d4c.tar.gz riscv-openocd-0801c66ff4cabfc44a7e89e8b798299c391a1d4c.tar.bz2 | |
Merge commit 'dfbbfac4d72e247e8094a49c8573b2f49689b6d5' into from_upstream
Change-Id: I6e7c0866291dd87946a4fd49d9bfe4cddefb3957
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/stm32f3x.cfg | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg index 4ecc7ed..aa978d9 100644 --- a/tcl/target/stm32f3x.cfg +++ b/tcl/target/stm32f3x.cfg @@ -24,6 +24,14 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x4000 } +# Allow overriding the Flash bank size +if { [info exists FLASH_SIZE] } { + set _FLASH_SIZE $FLASH_SIZE +} else { + # autodetect size + set _FLASH_SIZE 0 +} + # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz # # Since we may be running of an RC oscilator, we crank down the speed a @@ -63,7 +71,7 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME +flash bank $_FLASHNAME stm32f1x 0 $_FLASH_SIZE 0 0 $_TARGETNAME reset_config srst_nogate |