Age | Commit message (Collapse) | Author | Files | Lines | |
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2024-08-14 | Fit riscv-tests to newest riscv spec: renaming sptbr,sbadaddr,mbadaddr (#578) | HUJIYONG | 2 | -7/+7 | |
issue#577 In the newest riscv spec(2021 or later), two csr register "sptbr"(0x180) "s/mbadaddr"(0x243) were removed, and upgraded to "satp" "s/mtval". Together with more functions. This commit rename them to pass compile. | |||||
2024-03-19 | ma_addr: permit access faults in lieu of misaligned exceptions | Andrew Waterman | 1 | -1/+6 | |
2024-02-18 | Fix breakpoint test | Andrew Waterman | 1 | -0/+3 | |
See https://github.com/riscv/riscv-debug-spec/blob/f510a7dd33317d0eee0f26b4fa082cd43a5ac7ea/Sdtrig.tex#L213-L214 | |||||
2023-03-16 | Fix breakpoint.S failing when tcontrol is implemented (#463) | Luke Wren | 1 | -0/+10 | |
2022-12-07 | zicntr: separate cycle/instret accessibility test (#439) | Chih-Min Chao | 2 | -6/+58 | |
It is allowed that M-mode only implementation could skip cycle/instret if the Zicntr is not included. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2022-06-09 | Test misaligned stores. (#397) | Tim Newsome | 4 | -0/+125 | |
Assume that misaligned loads work correctly. Passes `make -C isa run` against spike (both with and without misaligned support). | |||||
2022-06-07 | Test misaligned loads. | Tim Newsome | 4 | -0/+126 | |
Cover lh, lw, and ld (only on rv64). | |||||
2022-05-28 | Permit mtval to be zero in misaligned address test, fixes #389 (#390) | Luke Wren | 1 | -0/+2 | |
2021-05-10 | Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support ↵ | SLAMET RIANTO | 1 | -0/+38 | |
CLIC mode. (#336) illegal.S: - After the test enters supervisor mode, check if paging is supported. - If paging is NOT supported (i.e. Bare S-mode), jump to a new section of code that checks the following: -- SFENCE.VMA causing illegal instruction trap regardless of TVM. -- Access to SATP does not trap. -- Jump to the same TSR check as regular S-mode -- End test sbreak.S & scall.S: - Before checking for scause, check if the core is in CLIC-mode (mtvec[1]). - If we're in CLIC-mode, mask off scause bits[(XLEN-1):8] before checing its value. - Otherwise, don't mask off any scause bits as in the original test. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com> | |||||
2021-01-08 | Don't rely on the implementation-specific WFI time limit (#318) | Paul Donahue | 1 | -18/+0 | |
* Bump riscv-test-env * Merge master * Don't assume that mscratch is initialized to a particular value on reset * Remove testcase that relies on the implementation-specific WFI time limit being 0. | |||||
2020-12-07 | Fix minor typo (#307) | Takahiro | 1 | -1/+1 | |
2020-11-20 | Only attempt to build tests supported by compiler | Andrew Waterman | 1 | -2/+0 | |
Resolves #303 | |||||
2019-07-29 | Support RV32E. Fixed #198 (#200) | Leway Colin | 1 | -5/+5 | |
2019-04-20 | masking no longer required. | Neel | 1 | -16/+0 | |
2019-04-20 | removing check for reset value of type in mcontrol | Neel | 1 | -10/+8 | |
2019-04-20 | fix for #159 #158 | Neel | 1 | -4/+7 | |
2018-12-18 | Avoid using t3 and t4 for supporting RV32E (#173) | zhonghochen | 1 | -5/+6 | |
2018-09-06 | Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) ↵ | Andrew Waterman | 1 | -1/+1 | |
(#159)" This reverts commit 901a2694d5384e4ef9af8e4fb0c9a07eb24d0028, under the advisement of @tommythorn in #158. | |||||
2018-09-06 | breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159) | Tommy Thorn | 1 | -1/+1 | |
2018-01-02 | Test access exception behavior for illegal addresses (#111) | Andrew Waterman | 2 | -0/+71 | |
OK'd by @palmer-dabbelt | |||||
2017-11-20 | Check mtval in rv64mi-p-illegal (#104) | Andrew Waterman | 1 | -0/+11 | |
Closes #103 | |||||
2017-11-11 | Make sure that code is 4-byte aligned before disabling rvc (#100) | Andrew Waterman | 1 | -0/+1 | |
2017-10-30 | Declare trap handlers as global symbols. (#87) | Richard Xia | 3 | -0/+4 | |
This allows them to be referenced by other files, such as a test environment that lives in a separate compilation unit. | |||||
2017-04-14 | Fix illegal-instruction test when S-mode is not implemented | Andrew Waterman | 1 | -10/+14 | |
2017-04-07 | Retrofit rv64mi-p-illegal to test vectored interrupts | Andrew Waterman | 1 | -7/+41 | |
2017-04-07 | Remove defunct IPI tests | Andrew Waterman | 2 | -52/+0 | |
2017-04-05 | Make ma_addr test work for systems with misaligned ld/st | Andrew Waterman | 1 | -34/+66 | |
2017-03-13 | Test mstatus.TW, mstatus.TVM, and mstatus.TSR features | Andrew Waterman | 1 | -1/+105 | |
2017-03-09 | Check mbadaddr in ma_addr test | Andrew Waterman | 1 | -0/+4 | |
2016-12-06 | avoid non-standard predefined macros | Andrew Waterman | 3 | -5/+5 | |
2016-08-26 | Update to new breakpoint & counter spec | Andrew Waterman | 1 | -26/+25 | |
2016-07-29 | Add an RVC test | Andrew Waterman | 2 | -3/+7 | |
2016-07-22 | Move dirty bit test to rv64si directory | Andrew Waterman | 2 | -94/+0 | |
Not sure this is quite right, since the test technically runs in M-mode. Also, remove unused rdnpc/example tests. | |||||
2016-07-11 | Remove instruction width assumptions to support RVC | Andrew Waterman | 2 | -0/+2 | |
2016-07-06 | Update to new PTE format | Andrew Waterman | 1 | -4/+4 | |
2016-06-17 | Fix breakpoint test when only one breakpoint present | Andrew Waterman | 1 | -1/+8 | |
2016-06-10 | Test more than one breakpoint at a time, if present | Andrew Waterman | 1 | -44/+68 | |
2016-06-09 | Update breakpoint spec | Andrew Waterman | 1 | -4/+19 | |
2016-06-08 | Don't arm breakpoint before setting break address | Andrew Waterman | 1 | -12/+11 | |
2016-06-08 | Add HW breakpoint test | Andrew Waterman | 2 | -0/+98 | |
2016-05-02 | Remove incorrect M-mode WFI test | Andrew Waterman | 2 | -9/+0 | |
MSIP isn't supposed to be writable locally! | |||||
2016-05-02 | Stop using tohost/fromhost registers | Andrew Waterman | 2 | -2/+15 | |
2016-04-30 | ERET -> xRET; new memory map | Andrew Waterman | 6 | -1118/+17 | |
For now, we no longer build hex files, because the programs don't start at address 0. This decision will likely be revisited. | |||||
2016-04-06 | Fix expected misa register value for RV32 | Andrew Waterman | 1 | -1/+1 | |
2016-03-10 | Add missing rv32mi/rv32si tests | Andrew Waterman | 2 | -3/+7 | |
2016-03-03 | Some S-mode tests really only belong in M-mode | Andrew Waterman | 2 | -8/+116 | |
2016-03-03 | WIP on priv spec v1.9 | Andrew Waterman | 4 | -7/+11 | |
2016-01-12 | Write 1, not 0, to MIPI | Andrew Waterman | 1 | -1/+1 | |
2015-11-16 | Update IPI test to work with new mechanism | Andrew Waterman | 1 | -17/+3 | |
2015-10-19 | Avoid REMU in timer test | Andrew Waterman | 1 | -2/+7 | |