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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-03-10 14:47:44 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-03-10 14:48:38 -0800 |
| commit | 057b1432679ded5dce4149797fa624205baee62e (patch) | |
| tree | 1b2787116f4e5c9633d1508301edfbdd674213e7 /isa/rv64mi | |
| parent | 31f39a39dffbdb810b18721bece5c233b91577eb (diff) | |
| download | riscv-tests-057b1432679ded5dce4149797fa624205baee62e.zip riscv-tests-057b1432679ded5dce4149797fa624205baee62e.tar.gz riscv-tests-057b1432679ded5dce4149797fa624205baee62e.tar.bz2 | |
Add missing rv32mi/rv32si tests
Diffstat (limited to 'isa/rv64mi')
| -rw-r--r-- | isa/rv64mi/dirty.S | 4 | ||||
| -rw-r--r-- | isa/rv64mi/mcsr.S | 6 |
2 files changed, 7 insertions, 3 deletions
diff --git a/isa/rv64mi/dirty.S b/isa/rv64mi/dirty.S index 731d80d..73d6c6c 100644 --- a/isa/rv64mi/dirty.S +++ b/isa/rv64mi/dirty.S @@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN # Try a faulting store to make sure dirty bit is not set li TESTNUM, 2 li t0, 1 - sd t0, dummy, t1 + sw t0, dummy, t1 # Load new page table li TESTNUM, 3 @@ -38,7 +38,7 @@ RVTEST_CODE_BEGIN sfence.vm # Try a non-faulting store to make sure dirty bit is set - sd t0, dummy, t1 + sw t0, dummy, t1 # Make sure R and D bits are set lw t0, page_table_2 diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S index 8a451ca..2eeb14c 100644 --- a/isa/rv64mi/mcsr.S +++ b/isa/rv64mi/mcsr.S @@ -13,8 +13,12 @@ RVTEST_RV64M RVTEST_CODE_BEGIN - # Check that mcpuid reports RV64 + # Check that mcpuid reports the correct XLEN +#ifdef __riscv64 TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62) +#else + TEST_CASE(2, a0, 0x0, csrr a0, misa; srl a0, a0, 30) +#endif # Check that mhartid reports 0 TEST_CASE(3, a0, 0x0, csrr a0, mhartid) |