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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-07-29 13:59:33 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-07-29 14:00:48 -0700 |
| commit | 84ffef7369bff65a60034ed847d3813ea8bc9c90 (patch) | |
| tree | 7be5af8643eb8eaf2356b8dae9784612c8dc0c48 /isa/rv64mi | |
| parent | 7b3fcbe9a9d336b67b914b842ff656aaafe7d939 (diff) | |
| download | riscv-tests-84ffef7369bff65a60034ed847d3813ea8bc9c90.zip riscv-tests-84ffef7369bff65a60034ed847d3813ea8bc9c90.tar.gz riscv-tests-84ffef7369bff65a60034ed847d3813ea8bc9c90.tar.bz2 | |
Add an RVC test
Diffstat (limited to 'isa/rv64mi')
| -rw-r--r-- | isa/rv64mi/breakpoint.S | 3 | ||||
| -rw-r--r-- | isa/rv64mi/ma_addr.S | 7 |
2 files changed, 7 insertions, 3 deletions
diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index 77c9509..b975331 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -36,9 +36,10 @@ RVTEST_CODE_BEGIN csrr a1, tdrdata1 andi a1, a1, 0x7ff bne a0, a1, 2f + .align 2 1: # Trap handler should skip this instruction. - j fail + beqz x0, fail # Make sure reads don't trap. li TESTNUM, 3 diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S index c84242a..6e7be94 100644 --- a/isa/rv64mi/ma_addr.S +++ b/isa/rv64mi/ma_addr.S @@ -13,9 +13,9 @@ RVTEST_RV64M RVTEST_CODE_BEGIN - .align 3 .option norvc - auipc s0, 0 + + la s0, data # indicate it's a load test li s1, CAUSE_MISALIGNED_LOAD @@ -80,6 +80,9 @@ RVTEST_CODE_END .data RVTEST_DATA_BEGIN +data: + .dword 0 + TEST_DATA RVTEST_DATA_END |