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| author | Andrew Waterman <andrew@sifive.com> | 2017-04-14 18:11:49 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-04-14 18:11:49 -0700 |
| commit | 0d53d12133bd3f7dce0e3731a5bc7dc0c1facc9d (patch) | |
| tree | 042a3ce59bea5d0f59f1c767959c17f7d828830c /isa/rv64mi | |
| parent | 2f4a65844606861aa2aec43db9a49997d0e02a5f (diff) | |
| download | riscv-tests-0d53d12133bd3f7dce0e3731a5bc7dc0c1facc9d.zip riscv-tests-0d53d12133bd3f7dce0e3731a5bc7dc0c1facc9d.tar.gz riscv-tests-0d53d12133bd3f7dce0e3731a5bc7dc0c1facc9d.tar.bz2 | |
Fix illegal-instruction test when S-mode is not implemented
Diffstat (limited to 'isa/rv64mi')
| -rw-r--r-- | isa/rv64mi/illegal.S | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S index 30105e6..a1b445f 100644 --- a/isa/rv64mi/illegal.S +++ b/isa/rv64mi/illegal.S @@ -21,6 +21,15 @@ bad2: .word 0 j fail + # Skip the rest of the test if S-mode is not present. + li t0, MSTATUS_MPP + csrc mstatus, t0 + li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S + csrs mstatus, t1 + csrr t2, mstatus + and t2, t2, t0 + bne t1, t2, pass + # Test vectored interrupts if they are supported. test_vectored_interrupts: csrwi mip, MIP_SSIP @@ -33,23 +42,18 @@ test_vectored_interrupts: csrsi mstatus, MSTATUS_MIE 1: j 1b - msip: csrw mtvec, s0 - # Skip the rest of the test if S-mode is not present. - li t0, MSTATUS_MPP - csrc mstatus, t0 - li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S - csrs mstatus, t1 - csrr t2, mstatus - and t2, t2, t0 - bne t1, t2, pass - # Delegate supervisor software interrupts so WFI won't stall. csrwi mideleg, MIP_SSIP + # Enter supervisor mode. la t0, 1f csrw mepc, t0 + li t0, MSTATUS_MPP + csrc mstatus, t0 + li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S + csrs mstatus, t1 mret 1: |