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2025-06-13Merge pull request #624 from riscv-software-src/ziccidHEADmasterAndrew Waterman3-2/+61
Add Ziccid test
2025-06-13Add Ziccid testAndrew Waterman3-2/+61
Requires latest Spike.
2025-06-12Replace floating magic constant by macro (#623)Andrew Waterman17-43/+61
* macro: define [sq]NaN[dfh] and [n]Inf[dfh] Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * apply sNaNf Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * apply sNaNd Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * apply qNaNd Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * apply qNaNf Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * apply sNaNh Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * apply Infh Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * apply nInfh Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * apply Infd Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * apply nInfd Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * apply Inff Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * apply nInff Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> --------- Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2025-06-10apply nInffChih-Min Chao4-4/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2025-06-10apply InffChih-Min Chao5-5/+5
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2025-06-10apply nInfdChih-Min Chao3-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2025-06-10apply InfdChih-Min Chao4-4/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2025-06-10apply nInfhChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2025-06-10apply InfhChih-Min Chao2-2/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2025-06-10apply sNaNhChih-Min Chao2-2/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2025-06-10apply qNaNfChih-Min Chao4-9/+9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2025-06-10apply qNaNdChih-Min Chao4-5/+5
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2025-06-10apply sNaNdChih-Min Chao3-5/+5
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2025-06-10apply sNaNfChih-Min Chao3-5/+5
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2025-06-10macro: define [sq]NaN[dfh] and [n]Inf[dfh]Chih-Min Chao1-0/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2025-04-28CI: Bump GitHub actions to latest versions (#619)Andrew Waterman2-11/+11
Co-authored-by: liangzhen <zhen.liang@spacemit.com>
2025-04-18Fix rv32ud-p-fcvt_w and -recoding being redundant with rv32ufAndrew Waterman3-3/+7
Resolves #614
2025-04-18configure: do autoupdateAriel Xiong1-4/+4
Signed-off-by: Ariel Xiong <ArielHeleneto@outlook.com>
2025-04-15Remove use of qNaN/sNaN in a different way to fix LLVM build (#613)Andrew Waterman9-69/+87
* Fix qNaN replacement in a more scalable way * Fix sNaN replacement in same manner as qNaN
2025-04-15Fix rv64ua-amomaxu_w and rv64ua-amominu_w testcases for rv32 (#611)etterli2-0/+8
Test case 6 of both rv64ua-amomaxu_w and rv64ua-amominu_w test a rv64 specific behaviour that the upper 32 bits must be ignored. This test does not apply for rv32 and this commits disables these tests for rv32.
2025-04-14Remove use of qNaN/sNaN to fix LLVM build (#612)Andrew Waterman9-22/+35
* Remove use of qNaN to fix LLVM build * Remove use of sNaN to fix LLVM build
2025-04-10Add test for pmpaddr[G-1] edge cases (#609)Tim Hutt4-0/+164
This adds a test for pmpaddr[G-1] edge cases. This bit is unusual because it has read legalisation that depends on another CSR. If the pmpcfg mode is OFF/TOR then it reads as 0. Otherwise it reads as its underlying value. Irrespective of pmpcfg it is always writable so you can always write it even when it reads as zero. Another edge case is when CSRS/C are used to modify a *different* bit and the underlying value of pmpaddr[G-1] is 1 but it reads as 0. The spec says "All CSR instructions atomically read-modify-write a single CSR" so even if these instructions don't directly modify pmpaddr[G-1] they do read it and then write it back, which will change its underlying value since it reads as 0.
2025-04-07Add instret_overflow testAndrew Waterman4-0/+52
See https://github.com/riscv/riscv-isa-manual/issues/1255 cc @Timmmm
2025-04-07Moving env forward (#607)Ariel Xiong1-0/+0
2025-04-03Removed irrelevant test (#605)Kathlene Magnus2-71/+0
2025-02-28Merge pull request #603 from riscv-software-src/bmark_compileJerry Zhao1-4/+11
Compile non-vec benchmarks for rv64gc
2025-02-24Compile non-vec benchmarks for rv64gcJerry Zhao1-4/+11
2025-02-07Added instructions to handle Rs1 and Rd dependency in load-store bypass ↵splinedrive1-0/+14
sequences. (#602)
2025-01-29Add Load-Store and Store-Load Bypass Tests for Forwarding in Pipelined CPU ↵splinedrive7-5/+301
(#600) - Enhanced test_macros.h with TEST_LD_ST_BYPASS and TEST_ST_LD_BYPASS macros to validate both load-store and store-load bypassing logic.
2024-11-18Suppress implicit-int and implicit-function-declaration warnings in ↵Tommy Murphy1-1/+1
Dhrystone which are non-fatal warnings in GCC 13 but fatal errors in GCC 14 (#587)
2024-11-16Fix the typo in the Makefrag for the reference to 2-stage-translation.S (#596)Kun Lu1-1/+1
2024-11-11Add hypervisor 2-stage translation test (#558)heiyuen19993-1/+147
* Create hypervisor Signed-off-by: heiyuen1999 <110437689+heiyuen1999@users.noreply.github.com> * Delete isa/hypervisor Signed-off-by: heiyuen1999 <110437689+heiyuen1999@users.noreply.github.com> * Create Makefrag Signed-off-by: heiyuen1999 <110437689+heiyuen1999@users.noreply.github.com> * Create 2-stage_translation.S set 2-stage translation, do a simple load and store Signed-off-by: heiyuen1999 <110437689+heiyuen1999@users.noreply.github.com> * Update Makefile add hypervisor to Makefile Signed-off-by: heiyuen1999 <110437689+heiyuen1999@users.noreply.github.com> * Update 2-stage_translation.S fix some error Signed-off-by: heiyuen1999 <110437689+heiyuen1999@users.noreply.github.com> * Update 2-stage_translation.S Signed-off-by: heiyuen1999 <110437689+heiyuen1999@users.noreply.github.com> * Update Makefrag Signed-off-by: heiyuen1999 <110437689+heiyuen1999@users.noreply.github.com> * Update Makefile Signed-off-by: heiyuen1999 <110437689+heiyuen1999@users.noreply.github.com> * Modify address alignment Modify address alignment to allow the page table to store 2048 entries Signed-off-by: heiyuen1999 <110437689+heiyuen1999@users.noreply.github.com> --------- Signed-off-by: heiyuen1999 <110437689+heiyuen1999@users.noreply.github.com>
2024-11-11[debug] Add sfence.vma in the disable_pmp (#537)lzbro2-0/+7
2024-11-11Merge pull request #535 from lz-bro/set_pmp_denyAnatoly Parshintsev3-0/+33
Set PMP to create invalid address
2024-11-09[debug] Set PMP to create bad addressliangzhen3-0/+33
2024-11-08[debug] Clear interrupt enable and pending in disable_timer (#538)lzbro2-1/+4
2024-10-31[debug] Support more SREC type in MemTestBlock (#589)lzbro1-3/+17
2024-10-31suppress new lint checks in old code (#590)Andrew Waterman1-0/+4
2024-09-06Merge pull request #581 from en-sc/en-sc/reserve-trigger-fix-propperEvgeniy Naydanov1-21/+59
[debug] Reserve triggers propperly in HwbpManual
2024-09-06[debug] Reserve triggers propperly in HwbpManualEvgeniy Naydanov1-21/+59
https://github.com/riscv-collab/riscv-openocd/pull/1111 introduces a change in OpenOCD behavior: a manual trigger should be manually removed to step/resume from it. This was not concidered in previous stop-gap solutions (76ff703d9161945354e334afa45c5dfe7680da60 and 8cc4918e904ca009cd85350fadf6f44e91eca13c) This commit: 1. Determines if `reserve trigger` is supported by the target. This can be removed once https://github.com/riscv-collab/riscv-openocd/pull/1111 is merged. 2. Marks `HwbpManual` test as not applicable in case `reserve trigger` is not supported. 3. Accounts for the change in OpenOCD's behavior when stepping from a manual BP. 4. Cleans up some minor mistakes in `HwbpManual`
2024-09-05Merge pull request #580 from en-sc/en-sc/reserve-trigger-fixEvgeniy Naydanov1-1/+1
[debug] Fix trigger reservation in HwbpManual
2024-09-05[debug] Fix trigger reservation in HwbpManualEvgeniy Naydanov1-1/+1
Syntax of the command was changed: (on/off) became compulsory.
2024-09-05Merge pull request #575 from en-sc/en-sc/reserve-triggerEvgeniy Naydanov1-0/+2
[debug] Reserve the trigger in `HwbpManual`
2024-08-27Fix EtriggerTest assuming that NULL causes a trap (#579)Luke Wren1-2/+4
There is already a mechanism for the test target to supply a known-bad address, so use that address if it is provided.
2024-08-14Fit riscv-tests to newest riscv spec: renaming sptbr,sbadaddr,mbadaddr (#578)HUJIYONG5-12/+12
issue#577 In the newest riscv spec(2021 or later), two csr register "sptbr"(0x180) "s/mbadaddr"(0x243) were removed, and upgraded to "satp" "s/mtval". Together with more functions. This commit rename them to pass compile.
2024-08-07[debug] Reserve the trigger in `HwbpManual`Evgeniy Naydanov1-0/+2
After https://github.com/riscv-collab/riscv-openocd/pull/1111 is merged, the registers a user wishes to have direct control of should be reserved. This is the case in `HwbpManual`. The test still works with older OpenOCD versions, since no exception is generated when a command (`riscv reserve_trigger` in this case) is not found.
2024-08-07Remove `debug/test` binary file (#574)Evgeniy Naydanov1-0/+0
The file was added by 00ab5f0dd4cf56b5a0551bc5adedf60c765d0c66 in #567. Seems like a mistake. ``` > readelf -h debug/test ELF Header: Magic: 7f 45 4c 46 02 01 01 00 00 00 00 00 00 00 00 00 Class: ELF64 Data: 2's complement, little endian Version: 1 (current) OS/ABI: UNIX - System V ABI Version: 0 Type: EXEC (Executable file) Machine: RISC-V Version: 0x1 Entry point address: 0x1212340000 Start of program headers: 64 (bytes into file) Start of section headers: 16552 (bytes into file) Flags: 0x0 Size of this header: 64 (bytes) Size of program headers: 56 (bytes) Number of program headers: 2 Size of section headers: 64 (bytes) Number of section headers: 18 Section header string table index: 17 ```
2024-07-30debug: update lds to merge more section (#573)Mark Zhuang2-6/+12
merge .bss.* to .bss then entry.S can clear it.
2024-07-17rsort.c description updated to Radix Sort instead of Quicksort (#572)Büşra Özdemir1-2/+2
2024-07-02README: add link to toolchain (#569)Daniel Maslowski1-1/+2
Signed-off-by: Daniel Maslowski <info@orangecms.org>
generated by cgit v1.1 at 2025-08-03 20:04:38 +0000