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2024-09-02Merge pull request #1788 from riscv-software-src/support-larger-addressesAndrew Waterman3-4/+7
2024-08-30Merge pull request #1779 from rtwfroody/trigger_timingAndrew Waterman1-1/+8
2024-08-29pointer masking: Always apply sstatus.MXR regardless of effective VYenHaoChen1-1/+1
2024-08-28pointer masking: Consider effective v bit instead of current v bitYenHaoChen1-1/+1
2024-08-27Merge pull request #1787 from riscv-software-src/fix-cfg-privJerry Zhao1-1/+1
2024-08-27Lift restriction on physical-address sizeAndrew Waterman2-2/+3
2024-08-27Check size_t bounds overflow in create_mem_regionAndrew Waterman1-2/+4
2024-08-27Merge pull request #1786 from YenHaoChen/pr-mcontrolAndrew Waterman2-6/+8
2024-08-27Use cmdline --priv flag when parsing proc configurations from DTBJerry Zhao1-1/+1
2024-08-27triggers: Let mcontrol.match be default (0/equal) if maskmax is 0YenHaoChen2-5/+6
2024-08-27triggers: mcontrol: refactor: Add mcontrol_t::maskmaxYenHaoChen2-1/+2
2024-08-26pointer masking: Pointer masking does not apply when MXR=1 regardless of MPRV...YenHaoChen1-1/+1
2024-08-23Fix exception priority for RV32E JAL/JALRAndrew Waterman3-0/+3
2024-08-23Fix exception priority for RV32E loads and AMOsAndrew Waterman1-1/+1
2024-08-23Refactor insn_template to be more DRYAndrew Waterman1-24/+23
2024-08-20For mcontrol6, default to BEFORE timing.Tim Newsome1-1/+8
2024-08-19Merge pull request #1771 from rtwfroody/match_maskAndrew Waterman1-4/+8
2024-08-19Fix mcontrol6 mask low/high operations.Tim Newsome1-4/+8
2024-08-18Merge pull request #1722 from ved-rivos/smdbltrpAndrew Waterman10-20/+92
2024-08-18pointer masking: refactor: Use xlen to avoid sketchy, hardcoded number 64YenHaoChen1-1/+2
2024-08-16pointer masking: Fix: Let transformed_addr of fetching be unchangedYenHaoChen1-4/+5
2024-08-12Fix a typo in https://github.com/riscv-software-src/riscv-isa-sim/pull/1721/c...YenHaoChen1-1/+1
2024-08-09Use ordered map for commit logAndrew Waterman1-1/+1
2024-08-07Add SmdbltrpVed Shanbhogue10-20/+92
2024-08-04Merge pull request #1758 from riscv-software-src/csr-init-fixesAndrew Waterman5-407/+398
2024-08-05Let MXR not affect implicit memory access for VS-stage address translationYenHaoChen1-1/+1
2024-08-01Only add CSRs if corresponding extensions are enabledAndrew Waterman1-55/+57
2024-08-01Remove boilerplate from most CSR instantiationsAndrew Waterman2-62/+34
2024-08-01Refactor initialization of mode-specific CSRsAndrew Waterman1-20/+18
2024-08-01Add CSRs through an interface, rather than mutating csrmapAndrew Waterman3-148/+156
2024-08-01Move CSR initialization to its own fileAndrew Waterman4-397/+408
2024-08-01In dtc_compile, use c string instead of stl stringAndrew Waterman1-3/+3
2024-08-01Improve dts <-> dtb APIAndrew Waterman3-9/+17
2024-08-01Merge pull request #1721 from abejgonzalez/dts_parsingAndrew Waterman7-135/+194
2024-08-01Merge pull request #1756 from riscv-software-src/clean-up-hpmAndrew Waterman3-17/+18
2024-08-01Fix enabling hypervisor extensionAndrew Waterman1-1/+1
2024-08-01Avoid magic constants in hpmcounter implementationAndrew Waterman3-17/+18
2024-08-01Fix trap interactive outputabejgonzalez1-11/+8
2024-08-01Generalize DTC compilation to support both DTS/Babejgonzalez3-43/+49
2024-08-01Support parsing procs fully from DTSJerry Zhao3-38/+97
2024-08-01Move isa property to a field of processor_t, not sim_tJerry Zhao6-32/+32
2024-08-01Pass cfg into make_dtsJerry Zhao3-18/+15
2024-08-01vcompress.vm: Check if there is any vector extension before using vector CSRsYenHaoChen1-4/+5
2024-07-31Fix segfault accessing menvcfg when U-mode doesn't existAndrew Waterman1-26/+30
2024-07-31vector: Check if there is any vector extension before using vector CSRsYenHaoChen14-33/+33
2024-07-31vnclip.wx: Check if there is any vector extension before using vector CSRsYenHaoChen1-3/+3
2024-07-24svpbmt: don't reset [mh]envcfg.pbmt to 1Chih-Min Chao1-4/+2
2024-07-22Merge pull request #1740 from YenHaoChen/pr-fcvtmod_w_dAndrew Waterman2-6/+7
2024-07-23fcvtmod.w.h: Not update fflags if no exception flag, e.g., exp == frac == 0YenHaoChen1-2/+1
2024-07-23refactor: set_fp_exceptions: Use a new macro raise_fp_exceptions(flags) and r...YenHaoChen1-4/+6
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