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| author | Andrew Waterman <andrew@sifive.com> | 2024-08-01 13:41:36 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-08-01 13:41:36 -0700 |
| commit | 39ba3fe46de71ba57225dd008579ade91509efea (patch) | |
| tree | c161e5bc1062cc0aa0233b7fc887ea9e1575e47d /riscv | |
| parent | 47a57eea738bc2cf11f133edf31375ee31165514 (diff) | |
| download | riscv-isa-sim-39ba3fe46de71ba57225dd008579ade91509efea.zip riscv-isa-sim-39ba3fe46de71ba57225dd008579ade91509efea.tar.gz riscv-isa-sim-39ba3fe46de71ba57225dd008579ade91509efea.tar.bz2 | |
Fix enabling hypervisor extension
I introduced a regression in #1753.
Resolves #1755
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 33f1dd4..4ac2222 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -417,7 +417,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) (proc->extension_enabled(EXT_ZICFISS) ? HENVCFG_SSE : 0) | (proc->extension_enabled(EXT_SSDBLTRP) ? HENVCFG_DTE : 0); henvcfg = std::make_shared<henvcfg_csr_t>(proc, CSR_HENVCFG, henvcfg_mask, 0, menvcfg); - if (proc->extension_enabled_const('H')) { + if (proc->extension_enabled('H')) { if (xlen == 32) { csrmap[CSR_HENVCFG] = std::make_shared<rv32_low_csr_t>(proc, CSR_HENVCFG, henvcfg); csrmap[CSR_HENVCFGH] = std::make_shared<rv32_high_csr_t>(proc, CSR_HENVCFGH, henvcfg); |