riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2025-12-09	Merge pull request #2166 from Steven-Li-Xiaogang/masterHEAD master	Andrew Waterman	1	-2/+2
2025-12-07	Merge pull request #2176 from riscv-software-src/fix-flq-fsq-big-endian	Andrew Waterman	4	-25/+6
2025-12-05	Fix Q extension on big-endian targets	Andrew Waterman	3	-24/+5
2025-12-05	Disable Q extension unless uint128_t is defined	Andrew Waterman	1	-1/+1
2025-12-04	Clean up VA size handling	Andrew Waterman	8	-52/+38
2025-12-01	Fix Svukte implementation	Andrew Waterman	2	-15/+23
2025-11-30	Merge pull request #2153 from chihminchao/enhance-zve	Andrew Waterman	22	-28/+55
2025-11-30	Merge pull request #2170 from binno/spelp_fix	Andrew Waterman	1	-2/+2
2025-11-30	SPELP field is defined only when S mode is enabled	Binno	1	-2/+2
2025-11-30	zve: correct the constraint for widening and floating configuraiton	Chih-Min Chao	1	-0/+10
2025-11-30	zve: correct the requirement for convension	Chih-Min Chao	12	-26/+26
2025-11-30	zve: some MUL operaiton are unavailable to zve64	Chih-Min Chao	8	-0/+16
2025-11-30	zve: relax zvfhmin and zvfh	Chih-Min Chao	1	-2/+3
2025-11-30	Eliminate the opcode cache	Andrew Waterman	2	-81/+47
2025-11-30	Rebuild opcode map whenever ISA/logging changes	Andrew Waterman	3	-1/+3
2025-11-29	Merge pull request #2162 from chihminchao/fix-zvfofp4min-contraint	Andrew Waterman	1	-2/+2
2025-11-29	Fix VS-mode check for sireg* (really vsireg*) CSRs	steven	1	-2/+2
2025-11-27	zvfofp4min: fix shared contraint with v[zs]ext	Chih-Min Chao	1	-2/+2
2025-11-26	csr: fix double trap state access	Chih-Min Chao	2	-6/+8
2025-11-26	csr: move menvcfg in front of mstatus	Chih-Min Chao	1	-17/+19
2025-11-25	zvfbfmin: fix contraint with zvfbfa	Chih-Min Chao	2	-2/+2
2025-11-21	Merge pull request #2158 from riscv-software-src/addrmem	Andrew Waterman	2	-4/+16
2025-11-20	Merge pull request #2157 from riscv-software-src/pmp	Andrew Waterman	1	-3/+6
2025-11-20	Memoize physical address/main-memory map	Andrew Waterman	2	-4/+16
2025-11-20	Fix PMP checks for misaligned accesses	Andrew Waterman	1	-3/+6
2025-11-20	Fix Zcf extension check in misa to require XLEN == 32	Nadime Barhoumi	1	-1/+1
2025-11-18	Merge pull request #2151 from riscv-software-src/speed-up-fetch	Andrew Waterman	12	-48/+108
2025-11-18	Allow TLB hits on LR/SC	Andrew Waterman	2	-6/+10
2025-11-18	Refactor shadow-stack use of xlate_flags_t	Andrew Waterman	1	-9/+5
2025-11-18	Add PTE cache to reduce TLB miss penalty	Andrew Waterman	2	-1/+30
2025-11-18	Remove unnecessary illegal-instruction checks	Andrew Waterman	3	-3/+0
2025-11-16	Move Zca-enabled check off the critical path	Andrew Waterman	4	-1/+19
2025-11-16	Avoid calling check_triggers when none are armed	Andrew Waterman	1	-9/+17
2025-11-16	Merge pull request #2149 from 5265325/fix/hartids	Andrew Waterman	1	-1/+1
2025-11-15	Fix collapse when setting hartids from command line.	Zhibo Hong	1	-1/+1
2025-11-15	Fix xtval when illegal instruction is triggered.	Zhibo Hong	1	-1/+1
2025-11-14	Merge pull request #2145 from nadime15/add-dm-no-abstractauto-flag	Andrew Waterman	2	-6/+7
2025-11-14	Remove else	Nadime Barhoumi	1	-6/+0
2025-11-13	Handle uncommon branch/jump exceptions with tail call	Andrew Waterman	3	-5/+8
2025-11-13	Use more conventional loop structure	Andrew Waterman	1	-12/+8
2025-11-13	Further speed up instruction fetch	Andrew Waterman	2	-4/+13
2025-11-13	Merge pull request #2147 from riscv-software-src/zicfilp-improvements	Andrew Waterman	7	-14/+20
2025-11-13	Fix potential landing pad escape	Andrew Waterman	1	-2/+1
2025-11-13	Handle uncommon JALR cases with a tail call	Andrew Waterman	6	-12/+19
2025-11-13	Update with generated encoding.h	Ved Shanbhogue	1	-1/+4
2025-11-13	Add Svrsw60t59b extension	Ved Shanbhogue	3	-1/+7
2025-11-13	Merge pull request #2146 from riscv-software-src/2144-redux	Andrew Waterman	1	-1/+2
2025-11-13	Move VI_LOOP_BASE out of VI_EXT_CHECK	Andrew Waterman	1	-2/+3
2025-11-13	small refactor of VI_EXT_CHECK to fix vl=0 cornercase	mslijepc	1	-2/+2
2025-11-13	Make abstractauto register optional in debug module	Nadime Barhoumi	2	-4/+11