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7 daysMerge pull request #2221 from DymShanks/fix/vu-mode-siregHEADmasterAndrew Waterman1-0/+4
9 daysFix: Enforce virtual_instruction trap for VU-mode indirect CSR accessDymShanks1-0/+4
9 daysClean up handling of ZcfAndrew Waterman1-0/+1
9 daysFactor out add_extension methodAndrew Waterman1-0/+3
9 daysZicfiss depends on ZaamoAndrew Waterman2-2/+0
13 daysMake reg_from_bytes a bit less grossAndrew Waterman1-22/+6
13 daysDRY in logging codeAndrew Waterman1-9/+4
13 daysFix triggers for accesses wider than XLENAndrew Waterman1-3/+2
14 dayscsrs.cc: if no U-mode, mstatus.tw is read-only 0pointerliu1-1/+2
2026-01-13Don't rely on definition of unratified bitmanip opcodesAndrew Waterman12-329/+385
2026-01-13Clean up grevi/gorci/shfli/unshfli implementationsAndrew Waterman4-29/+25
2026-01-03correct smcdeleg indirect CSRs address accessed via sireg*steven1-6/+8
2026-01-02Merge pull request #2191 from Steven-Li-Xiaogang/masterAndrew Waterman2-4/+6
2026-01-02fixed smcdeleg to be limited to, holds a value in the range 0x40-0x5F, from p...muhammad.moiz.hussain1-35/+38
2026-01-02changed minstret to instret and mcycle to cyclemuhammad.moiz.hussain2-18/+34
2026-01-02when AIA throw virt intruction exception and V=1 & vs-mode, otherwise throw i...muhammad.moiz.hussain1-1/+10
2025-12-31Merge pull request #2193 from mslijepc/mslijepc_20251224_zicclsmAndrew Waterman4-3/+2
2025-12-29removed cfg.misaligned optionmslijepc3-3/+1
2025-12-27Merge pull request #2197 from omerguzelelectronicguy/masterAndrew Waterman2-3/+5
2025-12-27Merge pull request #2161 from fkhaidari/fk/trig-algo-modAndrew Waterman4-75/+116
2025-12-26unnecessary dtb to dts operation removedÖmer Güzel2-3/+5
2025-12-25Update trigger behavior for memory accesses to match recommended debug specif...Farid Khaydari4-75/+116
2025-12-24Merge pull request #2194 from riscv-software-src/fix-2192Andrew Waterman1-1/+0
2025-12-24Remove declaration for undefined functionAndrew Waterman1-1/+0
2025-12-24added support for zicclsmmslijepc2-1/+2
2025-12-24register indirection CSRs 'iprio0~iprio15' when Smaia/Ssaia supportedsteven2-4/+6
2025-12-23Better to raise an illegal-instruction exception upon accessing sireg*steven1-5/+1
2025-12-17Fix infinite loop due to integer overflow in PMP checkAndrew Waterman1-4/+4
2025-12-11#2082 Reorder hstateen0 check for smcdelegMuhammad Moiz Hussain1-5/+3
2025-12-09Merge pull request #2166 from Steven-Li-Xiaogang/masterAndrew Waterman1-2/+2
2025-12-07Merge pull request #2176 from riscv-software-src/fix-flq-fsq-big-endianAndrew Waterman4-25/+6
2025-12-05Fix Q extension on big-endian targetsAndrew Waterman3-24/+5
2025-12-05Disable Q extension unless uint128_t is definedAndrew Waterman1-1/+1
2025-12-04Clean up VA size handlingAndrew Waterman8-52/+38
2025-12-01Fix Svukte implementationAndrew Waterman2-15/+23
2025-11-30Merge pull request #2153 from chihminchao/enhance-zveAndrew Waterman22-28/+55
2025-11-30Merge pull request #2170 from binno/spelp_fixAndrew Waterman1-2/+2
2025-11-30SPELP field is defined only when S mode is enabledBinno1-2/+2
2025-11-30zve: correct the constraint for widening and floating configuraitonChih-Min Chao1-0/+10
2025-11-30zve: correct the requirement for convensionChih-Min Chao12-26/+26
2025-11-30zve: some MUL operaiton are unavailable to zve64Chih-Min Chao8-0/+16
2025-11-30zve: relax zvfhmin and zvfhChih-Min Chao1-2/+3
2025-11-30Eliminate the opcode cacheAndrew Waterman2-81/+47
2025-11-30Rebuild opcode map whenever ISA/logging changesAndrew Waterman3-1/+3
2025-11-29Merge pull request #2162 from chihminchao/fix-zvfofp4min-contraintAndrew Waterman1-2/+2
2025-11-29Fix VS-mode check for sireg* (really vsireg*) CSRssteven1-2/+2
2025-11-27zvfofp4min: fix shared contraint with v[zs]extChih-Min Chao1-2/+2
2025-11-26csr: fix double trap state accessChih-Min Chao2-6/+8
2025-11-26csr: move menvcfg in front of mstatusChih-Min Chao1-17/+19
2025-11-25zvfbfmin: fix contraint with zvfbfaChih-Min Chao2-2/+2
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