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author | YenHaoChen <howard25336284@gmail.com> | 2024-08-28 11:34:57 +0800 |
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committer | YenHaoChen <howard25336284@gmail.com> | 2024-08-28 11:35:00 +0800 |
commit | 61d277c49c7843476abe671f05aa78f08e6278b2 (patch) | |
tree | 7d66413456b98d59ea2fc690c8b6d6d3224d87a3 /riscv | |
parent | 5029aa7ce84947d969fa7624b970ddfd026ee0b8 (diff) | |
download | riscv-isa-sim-61d277c49c7843476abe671f05aa78f08e6278b2.zip riscv-isa-sim-61d277c49c7843476abe671f05aa78f08e6278b2.tar.gz riscv-isa-sim-61d277c49c7843476abe671f05aa78f08e6278b2.tar.bz2 |
pointer masking: Consider effective v bit instead of current v bit
A previous commit removes the effectiveness of MPRV to MXR.
(https://github.com/riscv-software-src/riscv-isa-sim/pull/1784)
However, the removal implies the MPRV affects point masking
individually, and the MXR should consider the effective v bit.
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index e827f4a..ea86900 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -614,7 +614,7 @@ void mmu_t::register_memtracer(memtracer_t* t) } reg_t mmu_t::get_pmlen(bool effective_virt, reg_t effective_priv, xlate_flags_t flags) const { - if (!proc || proc->get_xlen() != 64 || (proc->state.sstatus->read() & MSTATUS_MXR) || flags.hlvx) + if (!proc || proc->get_xlen() != 64 || (proc->state.sstatus->readvirt(effective_virt) & MSTATUS_MXR) || flags.hlvx) return 0; reg_t pmm = 0; |