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authorTim Newsome <tim@casualhacker.net>2024-08-20 09:11:27 -0700
committerTim Newsome <tim@casualhacker.net>2024-08-20 09:11:27 -0700
commita1506ec006bad9c727652a5f7fbfe91c52572565 (patch)
tree047b8f70d4172ea7bcc8d93e1d604ade7a7c97f0 /riscv
parenta8c9d9ccb17e012f4eee5a664ff296d2aaa79d53 (diff)
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For mcontrol6, default to BEFORE timing.
The existing implementation would end up using AFTER even for instruction execute and data store triggers, which is not desirable.
Diffstat (limited to 'riscv')
-rw-r--r--riscv/triggers.cc9
1 files changed, 8 insertions, 1 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc
index 9eac968..5f3ffee 100644
--- a/riscv/triggers.cc
+++ b/riscv/triggers.cc
@@ -265,7 +265,14 @@ bool mcontrol_common_t::legalize_timing(reg_t val, reg_t timing_mask, reg_t sele
return TIMING_AFTER;
if (get_field(val, execute_mask))
return TIMING_BEFORE;
- return get_field(val, timing_mask);
+ if (timing_mask) {
+ // Use the requested timing.
+ return get_field(val, timing_mask);
+ } else {
+ // For mcontrol6 you can't request a timing. Default to before since that's
+ // most useful to the user.
+ return TIMING_BEFORE;
+ }
}
reg_t mcontrol6_t::tdata1_read(const processor_t * const proc) const noexcept {