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2024-03-06Zicfilp: Implement lpad insn behaviorMing-Yi Lai2-0/+10
2024-03-06Zicfilp: Check that the next insn is a lpad if ELP is LP_EXPECTEDMing-Yi Lai3-0/+19
2024-03-06Zicfilp: Add software_check(x) macro to throw a software check exceptionMing-Yi Lai2-0/+2
2024-03-06Zicfilp: Set ELP state when executing indirect jumpsMing-Yi Lai6-0/+35
2024-03-06Zicfilp: Add CSR fieldsMing-Yi Lai3-6/+28
2024-03-06Zicfilp: Add Zicfilp codes to riscv/encoding.hMing-Yi Lai2-1/+8
2024-03-06Zicfilp: Add Zicfilp extension flagMing-Yi Lai1-0/+1
2024-03-03Explicitly capture "this" in lambdasAndrew Waterman1-2/+2
2024-03-03Don't include subproject headers with -IAndrew Waterman1-1/+1
2024-03-01Merge pull request #1583 from rbuchner-aril/rbuchner/designated-initializersJerry Zhao2-28/+16
2024-02-19Merge pull request #1602 from YenHaoChen/pr-c_luiAndrew Waterman1-1/+1
2024-02-19Merge pull request #1610 from YenHaoChen/pr-wfiAndrew Waterman1-5/+3
2024-02-19Raise illegal instruction instead of virtual instruction on WFI when TW=1 in ...YenHaoChen1-5/+3
2024-02-16Fix c.mop.N decodingYenHaoChen1-1/+1
2024-02-14Reduce NS16550 address space size to one pageAndrew Waterman1-0/+7
2024-02-07Merge pull request #1591 from YenHaoChen/pr-sstc-stceAndrew Waterman1-2/+4
2024-02-06Fix hvip.VSEIP and hvip.VSTIP, so they don't observe platform-specific interr...YenHaoChen4-11/+31
2024-02-06Teach Sstc to respect xenvcfg.STCEYenHaoChen1-2/+4
2024-01-24Use designated initiallizers to construct xlate_flags_t objectsrbuchner2-28/+16
2024-01-18vcpop.m, vfirst.m: delete unnecessary VSTART write.Hong Cheng2-2/+0
2024-01-17Merge pull request #1551 from YenHaoChen/pr-shfliJerry Zhao2-0/+2
2024-01-17Merge pull request #1315 from endeneer/cpus-cpu-mapJerry Zhao1-1/+5
2024-01-12Merge pull request #1564 from demin-han/masterAndrew Waterman1-0/+1
2024-01-11Fix vectored VS-level interruptsScott Johnson1-1/+1
2024-01-11Introduce adjusted_cause which I will reuse nextScott Johnson1-1/+2
2024-01-11Introduce interrupt_bit which I will reuse nextScott Johnson1-1/+2
2024-01-12Add missing log commit of mstatushdemin.han1-0/+1
2024-01-11Refactor put_csr to direct writedemin.han1-1/+1
2024-01-10fix merge issueVed Shanbhogue1-1/+0
2024-01-10fix merge issueVed Shanbhogue1-3/+0
2024-01-10Merge branch 'master' into zaamo_zalrscVed Shanbhogue1-0/+4
2024-01-10Add Zaamo and Zalrsc extensionsVed Shanbhogue2-1/+9
2024-01-10B=Zba+Zbb+ZbsVed Shanbhogue1-1/+6
2024-01-04typo: HPM counters consider previous privilege mode if changedYenHaoChen1-1/+1
2023-12-30Add srmcfg CSRVed Shanbhogue6-3/+47
2023-12-26zip and unzip of Zbkb require RV32YenHaoChen2-0/+2
2023-12-22Merge pull request #1476 from sycuricon/masterAndrew Waterman1-1/+1
2023-12-22typo: correct sstateen CSR addressYenHaoChen1-1/+1
2023-12-13Fix UB on signed overflow in mulh routineAndrew Waterman1-1/+1
2023-12-13build: fix broken configurephantom10031-1/+1
2023-12-12riscv: sim.cc: Consider cpu-map node in cpus nodeTan En De1-1/+5
2023-12-11Merge pull request #1313 from endeneer/fdt-parse-clint-sifiveJerry Zhao1-1/+1
2023-12-11Merge pull request #1314 from endeneer/fdt-parse-plic-sifiveJerry Zhao1-1/+2
2023-12-11Merge pull request #1448 from ved-rivos/adue_fixAndrew Waterman2-8/+19
2023-12-11riscv: sim.cc: Parse for "sifive,plic-1.0.0" if "riscv,plic0" is absentTan En De1-1/+2
2023-12-11riscv: sim.cc: Parse for "sifive,clint0" if "riscv,clint0" is absentTan En De1-1/+1
2023-12-11Merge pull request #1506 from riscv-software-src/fix-1505Jerry Zhao1-2/+2
2023-12-11Merge pull request #1526 from riscv-software-src/default_cfgJerry Zhao7-65/+60
2023-12-09fix fmvh_x_d.h rv32 sign-extendedMadman1-1/+1
2023-12-08Use brace initializers for debug_module_config_t defaultsJerry Zhao1-9/+9
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