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| author | Andrew Waterman <andrew@sifive.com> | 2023-12-22 18:39:26 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-12-22 18:39:26 -0800 |
| commit | f557404ceaf1c9a5cecf82a49e557dc5fbf4a728 (patch) | |
| tree | cf1a40d251327b9e1c54f8eb57e1f69a0c052e34 /riscv | |
| parent | e8d1f8d21c5ae8567d1ab4a4db366bcb9ed55995 (diff) | |
| parent | a93f8b8c5a3be8358fd2489d8828f1f7ae9833e6 (diff) | |
| download | riscv-isa-sim-f557404ceaf1c9a5cecf82a49e557dc5fbf4a728.zip riscv-isa-sim-f557404ceaf1c9a5cecf82a49e557dc5fbf4a728.tar.gz riscv-isa-sim-f557404ceaf1c9a5cecf82a49e557dc5fbf4a728.tar.bz2 | |
Merge pull request #1476 from sycuricon/master
Bump configure to autoconf 2.71
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv.ac | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/riscv.ac b/riscv/riscv.ac index e52c570..5785f27 100644 --- a/riscv/riscv.ac +++ b/riscv/riscv.ac @@ -24,7 +24,7 @@ AC_ARG_WITH(varch, [AS_HELP_STRING([--with-varch=vlen:128,elen:64], [Sets the default vector config])], AC_DEFINE_UNQUOTED([DEFAULT_VARCH], "$withval", [Default value for --varch switch]), - AC_DEFINE_UNQUOTED([DEFAULT_VARCH], ["vlen:128,elen:64"], [Default value for --varch switch])) + AC_DEFINE([DEFAULT_VARCH], ["vlen:128,elen:64"], [Default value for --varch switch])) AC_ARG_WITH(target, [AS_HELP_STRING([--with-target=riscv64-unknown-elf], |