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6 daysvcompress.vm: Check if there is any vector extension before using vector CSRsYenHaoChen1-4/+5
7 daysvector: Check if there is any vector extension before using vector CSRsYenHaoChen13-29/+29
8 daysvnclip.wx: Check if there is any vector extension before using vector CSRsYenHaoChen1-3/+3
2024-07-23fcvtmod.w.h: Not update fflags if no exception flag, e.g., exp == frac == 0YenHaoChen1-2/+1
2024-07-06Add SsdbltrpVed Shanbhogue3-0/+17
2024-06-13Adding Zilsd and Zcmlsd extensions (Load/store pair for RV32)Christian Herber6-8/+43
2024-06-11Separate RV32 and RV64 C instructions into separate filesAndrew Waterman8-33/+21
2024-06-11triggers: implement tcontrolYenHaoChen1-0/+1
Implement Debug spec Section 5.7.6. Trigger Control (tcontrol). This commit lets tcontrol be read-only 0 if number of triggers is 0.
2024-05-31Avoid checking ELP before every instruction fetchAndrew Waterman3-0/+3
Serialize after setting ELP. That way, we can hoist the check outside of the main simulation loop.
2024-05-23zicflip: fix [ms]ret behaviorChih-Min Chao2-2/+2
Based on Spec chapter 3.5 "An MRET or SRET instruction is used to return from a trap in M-mode or S-mode, respectively. When executing an xRET instruction, if xPP holds the value y, then ELP is set to the value of xPELP if yLPE is 1; otherwise, it is set to NO_LP_EXPECTED; xPELP is set to NO_LP_EXPECTED." The change follow the last statement after semicolon "xPELP is set to NO_LP_EXPECTED" Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2024-05-06Add Zawrs extensionVed Shanbhogue2-0/+7
2024-05-03Zfa: fix: fmaxm.q requires Q instead of D extensionYenHaoChen1-1/+1
2024-05-01Remove Zbpbo, Zpn, and Zpsfoperand implementationAndrew Waterman326-2153/+4
2024-04-18Add Zicfiss extension from CFI extension, v0.4.0SuHsien Ho10-1/+54
1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name. 2. Add new software exception with tval 3 for shadow stack. 3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d. 4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding. 5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page. 6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag. 7. Check special pte(xwr=010) of SS page.
2024-03-21Merge pull request #1582 from mylai-mtk/zicfilp-upstreamAndrew Waterman7-1/+30
Support Zicfilp
2024-03-11Update vcompress.vm to not write vstart with 0 upon completionrbuchner1-1/+1
Vmcompress.vm requires vstart==0, so writing vstart with 0 is redundant. To do this, spin off VI_LOOP_END_BASE from VI_LOOP_END. VI_LOOP_END will contain VI_LOOP_END_BASE as well as a write of 0 to vstart. See #1623 for full discussion.
2024-03-06Zicfilp: Preserve expected landing pad state on trapsMing-Yi Lai3-1/+12
2024-03-06Zicfilp: Implement lpad insn behaviorMing-Yi Lai1-0/+6
2024-03-06Zicfilp: Set ELP state when executing indirect jumpsMing-Yi Lai3-0/+12
2024-02-19Merge pull request #1602 from YenHaoChen/pr-c_luiAndrew Waterman1-1/+1
Fix c.mop.N decoding
2024-02-19Raise illegal instruction instead of virtual instruction on WFI when TW=1 in ↵YenHaoChen1-5/+3
VU-mode The previous implementation raises virtual instruction on WFI when TW=1 in VU-mode. According to the recent discussion, we expect an illegal instruction exception in this case. Reference: https://github.com/riscv/riscv-isa-manual/issues/1234
2024-02-16Fix c.mop.N decodingYenHaoChen1-1/+1
The c.mop.N only accepts rd={x1, x3, x5, x7, x9, x11, x13, x15}. The previous implemention incorrectly accepts additional rd={x17, x19, x21, x23, x25, x27, x29, x31}.
2024-01-18vcpop.m, vfirst.m: delete unnecessary VSTART write.Hong Cheng2-2/+0
2024-01-17Merge pull request #1551 from YenHaoChen/pr-shfliJerry Zhao2-0/+2
zip and unzip of Zbkb require RV32
2024-01-12Add missing log commit of mstatushdemin.han1-0/+1
Signed-off-by: demin.han <demin.han@starfivetech.com>
2024-01-11Refactor put_csr to direct writedemin.han1-1/+1
1. put_csr needs search 2. MSTATUS_MPV not written back for RV32 Signed-off-by: demin.han <demin.han@starfivetech.com>
2023-12-26zip and unzip of Zbkb require RV32YenHaoChen2-0/+2
2023-12-09fix fmvh_x_d.h rv32 sign-extendedMadman1-1/+1
Signed-off-by: Madman <1017747824@qq.com>
2023-12-08Add Zimop extensionAndrew Waterman2-0/+4
2023-11-16Fix FMVP.D.X implementationAndrew Waterman1-1/+1
Resolves #1507
2023-11-02add halfword width amo instructionsVed Shanbhogue20-20/+31
2023-10-30add byte width amo instructionsVed Shanbhogue10-0/+31
2023-10-18Spike support for the Zalasr extensionbrs8-0/+18
2023-10-18add zcmop extension instructionsVed Shanbhogue2-2/+7
2023-10-16vamo: remove instruction implementationChih-Min Chao36-72/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2023-09-01fix condition of executing cbo.inval as a flush operationviktoryou1-3/+3
Signed-off-by: viktoryou <143797577+viktoryou@users.noreply.github.com>
2023-06-19Zvk: Implement Zvksh, vector SM3 Hash FunctionEric Gouriou2-0/+99
Implement the Zvksh sub-extension, "ShangMi Suite: SM3 Hash Function Instructions": - vsm3me.vv, message expansion, - vsm3c.vi, compression rounds. This also introduces a SM3 specific header for common logic. Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Co-authored-by: Albert Jakieła <aja@semihalf.com> Co-authored-by: Kornel Dulęba <mindal@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvksed, vector SM4 Block CipherEric Gouriou4-1/+140
Implement the Zvksed sub-extension, "ShangMi Suite: SM4 Block Cipher": - vsm4k.vi, vector SM4 key expansion, - vsm4r.{vs,vv}, vector SM4 rounds. This also introduces a header for common vector SM4 logic. Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Co-authored-by: Albert Jakieła <aja@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvkned, vector AES single roundEric Gouriou11-0/+502
Implement the Zvkned extension, "NIST Suite: Vector AES Encryption & Decryption (Single Round)". - vaeskf1.vi: AES forward key scheduling, AES-128. - vaeskf2.vi: AES forward key scheduling, AES-256. - vaesz.vs: AES encryption/decryption, 0-th round. - vaesdm.{vs,vv}: AES decryption, middle rounds. - vaesdf.{vs,vv}: AES decryption, final round. - vaesem.{vs,vv}: AES encryption, middle rounds. - vaesef.{vs,vv}: AES encryption, final round. An extension specific header containing common logic is added. Co-authored-by: Stanislaw Kardach <kda@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvknh[ab], NIST Suite: Vector SHA-2Eric Gouriou3-0/+186
Implement the instructions part of the Zvknha and Zvknhb sub-extensions: - vsha2ms.vv, message schedule - vsha2ch.vv / vsha2cl.vv, compression rounds A header files for common macros is added. Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvkg, Vector GCM/GMAC instructionEric Gouriou2-0/+70
Implement the proposed instruction in Zvkg, vghmac.vv, Vector Carryless Multiply Accumulate over GHASH Galois-Field. The instruction performs one step of GHASH routine as described in "NIST Special Publication 800-38D" a.k.a the AES-GCM specification. The logic was written to closely track the pseudo-code in the Zvk specification. Signed-off-by: Eric Gouriou <ego@rivosinc.com> Co-authored-by: Kornel Duleba <mindal@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvbc extension, vectory carryless multiplactionEric Gouriou4-0/+80
Implement the Zvbc instructions - vclmul.{vv,vx}, vector carryless multiply low - vclmulh.{vv,vx}, vector carryless multiply high Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvbb, Vector Bit-manipulation for CryptographyEric Gouriou16-0/+239
Implement the proposed instructions in Zvbb: - vandn.{vv,vx}, vector bitwise and-not - vbrev.v, vector bit reverse in element - vbrev8.v, vector bit reverse in bytes - vrev8.v, vector byte reverse - vctz.v, vector count trailing zeros - vclz.v, vector count leading zeros - vcpop.v, vector population count - vrol.{vv,vx}, vector rotate left - vror.{vi,vv,vx}, vector rotate right - vwsll.{vi,vv,vx} vector widening shift left logical A new instruction field, 'zimm6', is introduced, encoded in bits [15, 19] and [26].. It is used by "vror.vi" to encode a shift immediate in [0, 63]. Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Co-authored-by: Stanislaw Kardach <kda@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Implement Zacas extension.Gianluca Guida3-0/+73
2023-06-18Remove Xbitmanip from instructions that belong to multiple extensionsAndrew Waterman14-30/+16
2023-06-18Remove instructions that belong only to XbitmanipAndrew Waterman45-347/+0
2023-06-06Merge pull request #1321 from plctlab/plct-bf16-devAndrew Waterman10-4/+34
Add support for BF16 extensions
2023-06-01dscr.ebreakh is now dcsr.ebreakv[su]Tim Newsome2-8/+12
This change was made ages ago in the spec. I did not actually test that the new privilege checks in ebreak and c.ebreak are correct, but all the existing debug tests still pass.
2023-05-29Add flh/fsh/fmv_h_x/fmv_x_h instructions to Zvfbfmin/Zvfbfwma extensionsWeiwei Li4-4/+4
2023-05-29Add support for new instructions of Zvfbfwma extensionWeiwei Li2-0/+10
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