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| author | YenHaoChen <howard25336284@gmail.com> | 2024-07-22 17:50:54 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2024-07-23 09:10:22 +0800 |
| commit | e86e653ef35fcd6de8bb2ebe701dccdb9f30a6c7 (patch) | |
| tree | f3a507f8193d9bedcad3b9a83995e41a4bd72026 /riscv/insns | |
| parent | 1342c687f2b0429b3b185c9f11080300ca14529e (diff) | |
| download | riscv-isa-sim-e86e653ef35fcd6de8bb2ebe701dccdb9f30a6c7.zip riscv-isa-sim-e86e653ef35fcd6de8bb2ebe701dccdb9f30a6c7.tar.gz riscv-isa-sim-e86e653ef35fcd6de8bb2ebe701dccdb9f30a6c7.tar.bz2 | |
fcvtmod.w.h: Not update fflags if no exception flag, e.g., exp == frac == 0
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/fcvtmod_w_d.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/riscv/insns/fcvtmod_w_d.h b/riscv/insns/fcvtmod_w_d.h index e39400d..231f605 100644 --- a/riscv/insns/fcvtmod_w_d.h +++ b/riscv/insns/fcvtmod_w_d.h @@ -55,6 +55,5 @@ if (exp == 0) { } WRITE_RD(sext32(frac)); -STATE.fflags->write(STATE.fflags->read() | - (inexact ? softfloat_flag_inexact : 0) | +raise_fp_exceptions((inexact ? softfloat_flag_inexact : 0) | (invalid ? softfloat_flag_invalid : 0)); |