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| author | Ved Shanbhogue <ved@rivosinc.com> | 2024-05-04 15:30:10 -0500 |
|---|---|---|
| committer | Ved Shanbhogue <ved@rivosinc.com> | 2024-05-06 18:21:06 -0500 |
| commit | c5229c3f5f4b6404977bb4134f1a0bda5207ff90 (patch) | |
| tree | fd9c817dd725bd138d80782915b59379b809780f /riscv/insns | |
| parent | 7438d1e69286470b7aaa0a713fd853fdf5c12416 (diff) | |
| download | riscv-isa-sim-c5229c3f5f4b6404977bb4134f1a0bda5207ff90.zip riscv-isa-sim-c5229c3f5f4b6404977bb4134f1a0bda5207ff90.tar.gz riscv-isa-sim-c5229c3f5f4b6404977bb4134f1a0bda5207ff90.tar.bz2 | |
Add Zawrs extension
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/wrs_nto.h | 6 | ||||
| -rw-r--r-- | riscv/insns/wrs_sto.h | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/riscv/insns/wrs_nto.h b/riscv/insns/wrs_nto.h new file mode 100644 index 0000000..710e670 --- /dev/null +++ b/riscv/insns/wrs_nto.h @@ -0,0 +1,6 @@ +if (get_field(STATE.mstatus->read(), MSTATUS_TW)) { + require_privilege(PRV_M); +} else if (STATE.v) { + if (get_field(STATE.hstatus->read(), HSTATUS_VTW)) + require_novirt(); +} diff --git a/riscv/insns/wrs_sto.h b/riscv/insns/wrs_sto.h new file mode 100644 index 0000000..4e71aa0 --- /dev/null +++ b/riscv/insns/wrs_sto.h @@ -0,0 +1 @@ +// WRS.STO stalls for a short duration |