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| author | Ved Shanbhogue <ved@rivosinc.com> | 2024-06-20 09:08:32 -0500 |
|---|---|---|
| committer | Ved Shanbhogue <ved@rivosinc.com> | 2024-07-06 08:40:08 -0500 |
| commit | 0797c21001791ce31ffc871c8f3ab6964d901a30 (patch) | |
| tree | a13242d7aad2c11747b4c571e1181c5cf319acb4 /riscv/insns | |
| parent | 4a2da916671d49d9ab82f702f50995c19110c2a3 (diff) | |
| download | riscv-isa-sim-0797c21001791ce31ffc871c8f3ab6964d901a30.zip riscv-isa-sim-0797c21001791ce31ffc871c8f3ab6964d901a30.tar.gz riscv-isa-sim-0797c21001791ce31ffc871c8f3ab6964d901a30.tar.bz2 | |
Add Ssdbltrp
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/dret.h | 6 | ||||
| -rw-r--r-- | riscv/insns/mret.h | 4 | ||||
| -rw-r--r-- | riscv/insns/sret.h | 7 |
3 files changed, 17 insertions, 0 deletions
diff --git a/riscv/insns/dret.h b/riscv/insns/dret.h index bdcf3db..60aaf21 100644 --- a/riscv/insns/dret.h +++ b/riscv/insns/dret.h @@ -7,6 +7,12 @@ p->set_privilege(STATE.dcsr->prv, STATE.dcsr->v); if (STATE.prv < PRV_M) STATE.mstatus->write(STATE.mstatus->read() & ~MSTATUS_MPRV); +if (STATE.dcsr->prv == PRV_U || STATE.dcsr->v) + STATE.mstatus->write(STATE.mstatus->read() & ~MSTATUS_SDT); + +if (STATE.dcsr->v && STATE.dcsr->prv == PRV_U) + STATE.vsstatus->write(STATE.vsstatus->read() & ~SSTATUS_SDT); + /* We're not in Debug Mode anymore. */ STATE.debug_mode = false; diff --git a/riscv/insns/mret.h b/riscv/insns/mret.h index 3fe920c..140ebde 100644 --- a/riscv/insns/mret.h +++ b/riscv/insns/mret.h @@ -13,6 +13,10 @@ if (ZICFILP_xLPE(prev_virt, prev_prv)) { STATE.elp = static_cast<elp_t>(get_field(s, MSTATUS_MPELP)); } s = set_field(s, MSTATUS_MPELP, elp_t::NO_LP_EXPECTED); +if (prev_prv == PRV_U || prev_virt) + s = set_field(s, MSTATUS_SDT, 0); +if (prev_virt && prev_prv == PRV_U) + STATE.vsstatus->write(STATE.vsstatus->read() & ~SSTATUS_SDT); STATE.mstatus->write(s); if (STATE.mstatush) STATE.mstatush->write(s >> 32); // log mstatush change STATE.tcontrol->write((STATE.tcontrol->read() & CSR_TCONTROL_MPTE) ? (CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE) : 0); diff --git a/riscv/insns/sret.h b/riscv/insns/sret.h index 23a13b5..fe007d3 100644 --- a/riscv/insns/sret.h +++ b/riscv/insns/sret.h @@ -27,5 +27,12 @@ if (ZICFILP_xLPE(prev_virt, prev_prv)) { STATE.elp = static_cast<elp_t>(get_field(s, SSTATUS_SPELP)); } s = set_field(s, SSTATUS_SPELP, elp_t::NO_LP_EXPECTED); + +if (STATE.prv == PRV_S) { + s = set_field(s, SSTATUS_SDT, 0); + if (!STATE.v && prev_virt && prev_prv == PRV_U) + STATE.vsstatus->write(STATE.vsstatus->read() & ~SSTATUS_SDT); +} + STATE.sstatus->write(s); p->set_privilege(prev_prv, prev_virt); |