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| author | YenHaoChen <howard25336284@gmail.com> | 2024-06-11 09:27:33 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2024-06-11 10:21:41 +0800 |
| commit | db762327efe1c754081f7cbfa1f1cae168fedf17 (patch) | |
| tree | 12e630767dc32521f50ffb1ed22b0089b43795a0 /riscv/insns | |
| parent | 00dfa28cd71326a9b553052bf0160cb76f0e7e07 (diff) | |
| download | riscv-isa-sim-db762327efe1c754081f7cbfa1f1cae168fedf17.zip riscv-isa-sim-db762327efe1c754081f7cbfa1f1cae168fedf17.tar.gz riscv-isa-sim-db762327efe1c754081f7cbfa1f1cae168fedf17.tar.bz2 | |
triggers: implement tcontrol
Implement Debug spec Section 5.7.6. Trigger Control (tcontrol).
This commit lets tcontrol be read-only 0 if number of triggers is 0.
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/mret.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/insns/mret.h b/riscv/insns/mret.h index 6d4d59f..3fe920c 100644 --- a/riscv/insns/mret.h +++ b/riscv/insns/mret.h @@ -15,4 +15,5 @@ if (ZICFILP_xLPE(prev_virt, prev_prv)) { s = set_field(s, MSTATUS_MPELP, elp_t::NO_LP_EXPECTED); STATE.mstatus->write(s); if (STATE.mstatush) STATE.mstatush->write(s >> 32); // log mstatush change +STATE.tcontrol->write((STATE.tcontrol->read() & CSR_TCONTROL_MPTE) ? (CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE) : 0); p->set_privilege(prev_prv, prev_virt); |