riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-01-31	Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220130' into s...	Peter Maydell	13	-333/+712
2022-01-29	Merge remote-tracking branch 'remotes/quintela-gitlab/tags/migration-20220128...	Peter Maydell	3	-7/+0
2022-01-28	target/ppc: Remove support for the PowerPC 602 CPU	Cédric Le Goater	10	-322/+1
2022-01-28	Remove unnecessary minimum_version_id_old fields	Peter Maydell	3	-7/+0
2022-01-28	target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp	Peter Maydell	1	-2/+2
2022-01-28	target/arm: Log CPU index in 'Taking exception' log	Peter Maydell	3	-5/+8
2022-01-28	target/ppc: 74xx: Set SRRs directly in exception code	Fabiano Rosas	1	-11/+2
2022-01-28	target/ppc: 74xx: System Reset interrupt cleanup	Fabiano Rosas	1	-16/+2
2022-01-28	target/ppc: 74xx: System Call exception cleanup	Fabiano Rosas	1	-6/+11
2022-01-28	target/ppc: 74xx: Program exception cleanup	Fabiano Rosas	1	-4/+0
2022-01-28	target/ppc: 74xx: External interrupt cleanup	Fabiano Rosas	1	-38/+0
2022-01-28	target/ppc: 74xx: Machine Check exception cleanup	Fabiano Rosas	1	-24/+0
2022-01-28	target/ppc: Simplify powerpc_excp_74xx	Fabiano Rosas	1	-202/+9
2022-01-28	target/ppc: Introduce powerpc_excp_74xx	Fabiano Rosas	1	-0/+474
2022-01-28	target/ppc: books: Program exception cleanup	Fabiano Rosas	1	-4/+0
2022-01-28	target/ppc: books: External interrupt cleanup	Fabiano Rosas	1	-23/+7
2022-01-28	target/ppc: books: Machine Check exception cleanup	Fabiano Rosas	1	-17/+0
2022-01-28	target/ppc: Simplify powerpc_excp_books	Fabiano Rosas	1	-147/+14
2022-01-28	target/ppc: Introduce powerpc_excp_books	Fabiano Rosas	1	-0/+478
2022-01-28	target/ppc: 405: Watchdog timer exception cleanup	Fabiano Rosas	1	-9/+0
2022-01-28	target/ppc: 405: Program exception cleanup	Fabiano Rosas	1	-15/+4
2022-01-28	target/ppc: 405: Instruction storage interrupt cleanup	Fabiano Rosas	1	-1/+0
2022-01-28	target/ppc: 405: Data Storage exception cleanup	Fabiano Rosas	1	-1/+1
2022-01-28	target/ppc: 405: Debug exception cleanup	Fabiano Rosas	1	-14/+4
2022-01-28	target/ppc: 405: Alignment exception cleanup	Fabiano Rosas	1	-7/+0
2022-01-28	target/ppc: 405: System call exception cleanup	Fabiano Rosas	1	-19/+2
2022-01-28	target/ppc: 405: External exception cleanup	Fabiano Rosas	1	-37/+0
2022-01-28	target/ppc: 405: Machine check exception cleanup	Fabiano Rosas	1	-24/+2
2022-01-28	target/ppc: 405: Critical exceptions cleanup	Fabiano Rosas	1	-15/+2
2022-01-28	target/ppc: Simplify powerpc_excp_40x	Fabiano Rosas	1	-195/+10
2022-01-28	target/ppc: Introduce powerpc_excp_40x	Fabiano Rosas	1	-0/+474
2022-01-28	target/ppc: 405: Add missing MSR_ME bit	Fabiano Rosas	1	-0/+1
2022-01-28	target/ppc: 405: Rename MSR_POW to MSR_WE	Fabiano Rosas	2	-1/+2
2022-01-28	ppc/ppc405: Fix TLB flushing	Cédric Le Goater	3	-2/+13
2022-01-28	target/ppc: Put do_rfi under a TCG-only block	Fabiano Rosas	1	-2/+0
2022-01-28	target/ppc: Fix test on mmu_model in hreg_compute_hflags_value()	Cédric Le Goater	1	-2/+4
2022-01-28	target/ppc: fix 'skip KVM' cond in cpu_interrupt_exittb()	Daniel Henrique Barboza	1	-1/+5
2022-01-28	target/ppc/mmu_common: Fix SRR1/MSR error code on Book-E	Vitaly Cheptsov	1	-3/+15
2022-01-28	target/ppc: 603: fix restore of GPRs 0-3 on rfi	Christophe Leroy	1	-0/+4
2022-01-21	target/riscv: Relax UXL field for debugging	LIU Zhiwei	1	-4/+4
2022-01-21	target/riscv: Enable uxl field write	LIU Zhiwei	2	-6/+25
2022-01-21	target/riscv: Set default XLEN for hypervisor	LIU Zhiwei	1	-0/+10
2022-01-21	target/riscv: Adjust scalar reg in vector with XLEN	LIU Zhiwei	1	-1/+1
2022-01-21	target/riscv: Adjust vector address with mask	LIU Zhiwei	1	-10/+15
2022-01-21	target/riscv: Fix check range for first fault only	LIU Zhiwei	1	-2/+2
2022-01-21	target/riscv: Remove VILL field in VTYPE	LIU Zhiwei	1	-1/+0
2022-01-21	target/riscv: Adjust vsetvl according to XLEN	LIU Zhiwei	2	-2/+10
2022-01-21	target/riscv: Split out the vill from vtype	LIU Zhiwei	5	-6/+19
2022-01-21	target/riscv: Split pm_enabled into mask and base	LIU Zhiwei	3	-23/+16
2022-01-21	target/riscv: Calculate address according to XLEN	LIU Zhiwei	5	-69/+21