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| author | Fabiano Rosas <farosas@linux.ibm.com> | 2022-01-28 13:15:03 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-01-28 13:15:03 +0100 |
| commit | 301e5d48b15d2846cabe0f5c7600860b35c58c12 (patch) | |
| tree | e09b8d2f7f82a9f160b1dabaad8cf13f763b66eb /target | |
| parent | 645d843ca55f0a7aa9be3ef19694d5a44b002f6e (diff) | |
| download | qemu-301e5d48b15d2846cabe0f5c7600860b35c58c12.zip qemu-301e5d48b15d2846cabe0f5c7600860b35c58c12.tar.gz qemu-301e5d48b15d2846cabe0f5c7600860b35c58c12.tar.bz2 | |
target/ppc: 405: Add missing MSR_ME bit
The 405 MSR has the Machine Check Enable bit. We're making use of it
when dispatching Machine Check, so add the bit to the msr_mask.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220118184448.852996-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/cpu_init.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index e63705b..23a1303 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2540,6 +2540,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data) (1ull << MSR_EE) | (1ull << MSR_PR) | (1ull << MSR_FP) | + (1ull << MSR_ME) | (1ull << MSR_DWE) | (1ull << MSR_DE) | (1ull << MSR_IR) | |