riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
5 days	target/xtensa: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	1	-7/+5
5 days	target/tricore: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	1	-1/+1
5 days	target/sparc: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	1	-1/+3
5 days	target/sh4: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	1	-2/+2
5 days	target/s390x: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	4	-24/+23
5 days	target/s390x: Restrict I/O handler installers to system emulation	Philippe Mathieu-Daudé	1	-0/+2
5 days	target/rx: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	1	-1/+1
5 days	target/riscv: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	2	-6/+6
5 days	target/ppc: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	1	-1/+3
5 days	target/openrisc: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	1	-1/+3
5 days	target/mips: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	2	-3/+5
5 days	target/microblaze: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	1	-1/+3
5 days	target/m68k: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	1	-1/+3
5 days	target/loongarch: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	1	-5/+3
5 days	target/i386: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	2	-7/+5
5 days	target/hppa: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	1	-1/+3
5 days	target/hexagon: Remove CPUClass:has_work() handler	Philippe Mathieu-Daudé	1	-6/+0
5 days	target/avr: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	1	-1/+1
5 days	target/arm: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	1	-1/+3
5 days	target/alpha: Move has_work() from CPUClass to SysemuCPUOps	Philippe Mathieu-Daudé	1	-1/+3
5 days	target/arm: Prefer cached CpuClass over CPU_GET_CLASS() macro	Philippe Mathieu-Daudé	2	-4/+2
5 days	Merge tag 'pull-tcg-20250308' of https://gitlab.com/rth7680/qemu into staging	Stefan Hajnoczi	42	-24/+42
6 days	exec: Declare tlb_flush*() in 'exec/cputlb.h'	Philippe Mathieu-Daudé	26	-15/+26
6 days	exec: Declare tlb_set_page() in 'exec/cputlb.h'	Philippe Mathieu-Daudé	13	-6/+13
6 days	exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h'	Philippe Mathieu-Daudé	2	-2/+2
6 days	exec: Declare tlb_set_page_full() in 'exec/cputlb.h'	Philippe Mathieu-Daudé	1	-1/+1
6 days	Merge tag 'pull-target-arm-20250307' of https://git.linaro.org/people/pmaydel...	Stefan Hajnoczi	10	-141/+406
6 days	Merge tag 'pull-loongarch-20250307' of https://gitlab.com/gaosong/qemu into s...	Stefan Hajnoczi	6	-8/+68
7 days	target/rx: Remove TCG_CALL_NO_WG from helpers which write env	Keith Packard	1	-17/+17
7 days	target/rx: Set exception vector base to 0xffffff80	Keith Packard	1	-1/+1
7 days	target/arm: Make dummy debug registers RAZ, not NOP	Peter Maydell	1	-3/+4
7 days	target/arm: Drop unused address_offset from op_addr_{rr, ri}_post()	Peter Maydell	1	-13/+13
7 days	target/arm: Correct STRD atomicity	Peter Maydell	1	-20/+39
7 days	target/arm: Correct LDRD atomicity and fault behaviour	Peter Maydell	1	-24/+46
7 days	target/arm: Document the architectural names of our GTIMERs	Alex Bennée	1	-5/+5
7 days	target/arm: Implement SEL2 physical and virtual timers	Alex Bennée	4	-1/+172
7 days	target/arm: Refactor handling of timer offset for direct register accesses	Peter Maydell	3	-54/+62
7 days	target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses	Peter Maydell	1	-9/+27
7 days	target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled	Peter Maydell	1	-0/+3
7 days	target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer	Peter Maydell	1	-2/+0
7 days	target/arm: Apply correct timer offset when calculating deadlines	Peter Maydell	1	-2/+27
7 days	target/loongarch: check tlb_ps	Song Gao	6	-8/+56
7 days	target/loongarch: fix 'make check-functional' failed	Song Gao	1	-0/+12
7 days	Merge tag 'accel-cpus-20250306' of https://github.com/philmd/qemu into staging	Stefan Hajnoczi	51	-114/+152
8 days	target/i386: Mark WHPX APIC region as little-endian	Philippe Mathieu-Daudé	1	-1/+1
8 days	target/alpha: Do not mix exception flags and FPCR bits	Philippe Mathieu-Daudé	1	-8/+7
8 days	target/riscv: Convert misa_mxl_max using GLib macros	Philippe Mathieu-Daudé	1	-5/+5
8 days	target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL	Philippe Mathieu-Daudé	2	-2/+2
8 days	target/xtensa: Finalize config in xtensa_register_core()	Philippe Mathieu-Daudé	2	-3/+4
8 days	target/sparc: Constify SPARCCPUClass::cpu_def	Philippe Mathieu-Daudé	1	-1/+1