| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-06-26 | hw/riscv: Validate cluster and NUMA node boundary | Gavin Shan | 1 | -0/+2 |
| 2023-05-05 | hw/riscv: Add signature dump function for spike to run ACT tests | Weiwei Li | 1 | -0/+13 |
| 2023-02-16 | hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() | Daniel Henrique Barboza | 1 | -10/+1 |
| 2023-02-16 | hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel() | Daniel Henrique Barboza | 1 | -1/+2 |
| 2023-02-07 | hw/riscv: change riscv_compute_fdt_addr() semantics | Daniel Henrique Barboza | 1 | -1/+2 |
| 2023-02-07 | hw/riscv: split fdt address calculation from fdt load | Daniel Henrique Barboza | 1 | -3/+3 |
| 2023-02-07 | hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' | Daniel Henrique Barboza | 1 | -9/+9 |
| 2023-01-20 | hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() | Daniel Henrique Barboza | 1 | -1/+1 |
| 2023-01-20 | hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() | Daniel Henrique Barboza | 1 | -3/+3 |
| 2023-01-20 | hw/riscv/spike.c: simplify create_fdt() | Daniel Henrique Barboza | 1 | -3/+1 |
| 2023-01-20 | hw/riscv/boot.c: use MachineState in riscv_load_kernel() | Daniel Henrique Barboza | 1 | -2/+1 |
| 2023-01-20 | hw/riscv/boot.c: use MachineState in riscv_load_initrd() | Daniel Henrique Barboza | 1 | -2/+1 |
| 2023-01-20 | hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() | Daniel Henrique Barboza | 1 | -4/+5 |
| 2023-01-20 | hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() | Daniel Henrique Barboza | 1 | -8/+2 |
| 2023-01-20 | hw/riscv/spike.c: load initrd right after riscv_load_kernel() | Daniel Henrique Barboza | 1 | -16/+15 |
| 2023-01-20 | hw/riscv/spike: use 'fdt' from MachineState | Daniel Henrique Barboza | 1 | -7/+5 |
| 2023-01-20 | hw/riscv: spike: Decouple create_fdt() dependency to ELF loading | Bin Meng | 1 | -10/+51 |
| 2023-01-20 | hw/riscv/boot.c: introduce riscv_default_firmware_name() | Daniel Henrique Barboza | 1 | -9/+5 |
| 2023-01-20 | hw/riscv: spike: Remove the out-of-date comments | Bin Meng | 1 | -5/+0 |
| 2023-01-20 | hw/char: riscv_htif: Move registers from CPUArchState to HTIFState | Bin Meng | 1 | -2/+1 |
| 2023-01-20 | hw/char: riscv_htif: Drop useless assignment of memory region | Bin Meng | 1 | -3/+2 |
| 2023-01-06 | hw/riscv: spike: Remove misleading comments | Bin Meng | 1 | -1/+0 |
| 2022-10-17 | hw/riscv: set machine->fdt in spike_board_init() | Daniel Henrique Barboza | 1 | -0/+6 |
| 2022-09-07 | hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec() | Daniel Henrique Barboza | 1 | -1/+1 |
| 2022-05-24 | hw/riscv: Make CPU config error handling generous (virt/spike) | Tsukasa OI | 1 | -1/+1 |
| 2022-04-29 | hw/riscv: Don't add empty bootargs to device tree | Bin Meng | 1 | -1/+1 |
| 2022-04-29 | hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally | Bin Meng | 1 | -2/+3 |
| 2022-01-21 | hw/riscv: Remove macros for ELF BIOS image names | Anup Patel | 1 | -2/+2 |
| 2022-01-21 | hw/riscv: spike: Allow using binary firmware as bios | Anup Patel | 1 | -16/+25 |
| 2021-10-22 | hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id | Bin Meng | 1 | -4/+2 |
| 2021-09-21 | hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT | Anup Patel | 1 | -5/+9 |
| 2021-09-21 | hw/intc: Rename sifive_clint sources to riscv_aclint sources | Anup Patel | 1 | -1/+1 |
| 2021-08-26 | arch_init.h: Don't include arch_init.h unnecessarily | Peter Maydell | 1 | -1/+0 |
| 2021-06-08 | hw/riscv: Use macros for BIOS image names | Bin Meng | 1 | -4/+2 |
| 2021-06-08 | hw/riscv: Support the official CLINT DT bindings | Bin Meng | 1 | -1/+5 |
| 2021-05-02 | hw: Do not include qemu/log.h if it is not necessary | Thomas Huth | 1 | -1/+0 |
| 2021-03-09 | qtest: delete superfluous inclusions of qtest.h | Chen Qun | 1 | -1/+0 |
| 2021-03-04 | hw/riscv: Drop 'struct MemmapEntry' | Bin Meng | 1 | -6/+3 |
| 2021-01-16 | riscv: Pass RISCVHartArrayState by pointer | Alistair Francis | 1 | -4/+4 |
| 2020-12-17 | hw/riscv: Use the CPU to determine if 32-bit | Alistair Francis | 1 | -4/+4 |
| 2020-12-17 | hw/riscv: spike: Remove compile time XLEN checks | Alistair Francis | 1 | -21/+24 |
| 2020-12-17 | hw/riscv: boot: Remove compile time XLEN checks | Alistair Francis | 1 | -1/+2 |
| 2020-12-17 | riscv: spike: Remove target macro conditionals | Alistair Francis | 1 | -1/+1 |
| 2020-10-22 | hw/riscv: Load the kernel after the firmware | Alistair Francis | 1 | -3/+8 |
| 2020-09-09 | hw/riscv: Move riscv_htif model to hw/char | Bin Meng | 1 | -1/+1 |
| 2020-09-09 | hw/riscv: Move sifive_clint model to hw/intc | Bin Meng | 1 | -1/+1 |
| 2020-09-09 | hw/riscv: clint: Avoid using hard-coded timebase frequency | Bin Meng | 1 | -1/+2 |
| 2020-08-25 | hw/riscv: spike: Allow creating multiple NUMA sockets | Anup Patel | 1 | -74/+158 |
| 2020-08-25 | hw/riscv: Allow creating multiple instances of CLINT | Anup Patel | 1 | -1/+1 |
| 2020-08-21 | hw/riscv: spike: Change the default bios to use generic platform image | Bin Meng | 1 | -2/+7 |
