diff options
| author | Anup Patel <anup.patel@wdc.com> | 2021-08-31 16:36:00 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-09-21 07:56:49 +1000 |
| commit | cc63a18282d8e8cd96d8bf26c29cad2e879ff9f6 (patch) | |
| tree | fb80c03d14f5c335e4c65e28bad7781be9cd2ccb /hw/riscv/spike.c | |
| parent | ea6eaa0604d2ad66636f968842fe9ff315b065c8 (diff) | |
| download | qemu-cc63a18282d8e8cd96d8bf26c29cad2e879ff9f6.zip qemu-cc63a18282d8e8cd96d8bf26c29cad2e879ff9f6.tar.gz qemu-cc63a18282d8e8cd96d8bf26c29cad2e879ff9f6.tar.bz2 | |
hw/intc: Rename sifive_clint sources to riscv_aclint sources
We will be upgrading SiFive CLINT implementation into RISC-V ACLINT
implementation so let's first rename the sources.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210831110603.338681-2-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/spike.c')
| -rw-r--r-- | hw/riscv/spike.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index aae36f2..690c19c 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -35,7 +35,7 @@ #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" #include "hw/char/riscv_htif.h" -#include "hw/intc/sifive_clint.h" +#include "hw/intc/riscv_aclint.h" #include "chardev/char.h" #include "sysemu/device_tree.h" #include "sysemu/sysemu.h" |