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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-05-14 15:29:40 +0900 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-05-24 10:38:50 +1000 |
| commit | 4bcfc391ac627155448951b45a8432eab91c2db9 (patch) | |
| tree | fef6ef0b318066a6e4e1f5461a3c877462084fbc /hw/riscv/spike.c | |
| parent | a4a9a4432e2bf280a989ca344466d7375db7993f (diff) | |
| download | qemu-4bcfc391ac627155448951b45a8432eab91c2db9.zip qemu-4bcfc391ac627155448951b45a8432eab91c2db9.tar.gz qemu-4bcfc391ac627155448951b45a8432eab91c2db9.tar.bz2 | |
hw/riscv: Make CPU config error handling generous (virt/spike)
If specified CPU configuration is not valid, not just it prints error
message, it aborts and generates core dumps (depends on the operating
system). This kind of error handling should be used only when a serious
runtime error occurs.
This commit makes error handling on CPU configuration more generous on
virt/spike machines. It now just prints error message and quits (without
coredumps and aborts).
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <d17381d3ea4992808cf1894f379ca67220f61b45.1652509778.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/spike.c')
| -rw-r--r-- | hw/riscv/spike.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 068ba34..e41b6aa 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -230,7 +230,7 @@ static void spike_board_init(MachineState *machine) base_hartid, &error_abort); object_property_set_int(OBJECT(&s->soc[i]), "num-harts", hart_count, &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); /* Core Local Interruptor (timer and IPI) for each socket */ riscv_aclint_swi_create( |