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| author | Anup Patel <apatel@ventanamicro.com> | 2022-01-18 13:38:56 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:57 +1000 |
| commit | 092dc6df92f2f97487747eb1044ac2bcac64924d (patch) | |
| tree | 104bd6510c90bc4808f930c5e92ec0577d425ab5 /hw/riscv/spike.c | |
| parent | 8d8897accb1c9b28267b3c7eb402b6bc5d967f7e (diff) | |
| download | qemu-092dc6df92f2f97487747eb1044ac2bcac64924d.zip qemu-092dc6df92f2f97487747eb1044ac2bcac64924d.tar.gz qemu-092dc6df92f2f97487747eb1044ac2bcac64924d.tar.bz2 | |
hw/riscv: Remove macros for ELF BIOS image names
Now that RISC-V Spike machine can use BIN BIOS images, we remove
the macros used for ELF BIOS image names.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/spike.c')
| -rw-r--r-- | hw/riscv/spike.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 597df4c..d059a67 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -260,11 +260,11 @@ static void spike_board_init(MachineState *machine) */ if (riscv_is_32bit(&s->soc[0])) { firmware_end_addr = riscv_find_and_load_firmware(machine, - RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base, + RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base, htif_symbol_callback); } else { firmware_end_addr = riscv_find_and_load_firmware(machine, - RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base, + RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base, htif_symbol_callback); } |