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path: root/hw/riscv/spike.c
AgeCommit message (Expand)AuthorFilesLines
2024-02-09target/riscv: support new isa extension detection devicetree propertiesConor Dooley1-4/+2
2023-06-26hw/riscv: Validate cluster and NUMA node boundaryGavin Shan1-0/+2
2023-05-05hw/riscv: Add signature dump function for spike to run ACT testsWeiwei Li1-0/+13
2023-02-16hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()Daniel Henrique Barboza1-10/+1
2023-02-16hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()Daniel Henrique Barboza1-1/+2
2023-02-07hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza1-1/+2
2023-02-07hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza1-3/+3
2023-02-07hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms'Daniel Henrique Barboza1-9/+9
2023-01-20hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()Daniel Henrique Barboza1-1/+1
2023-01-20hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id()Daniel Henrique Barboza1-3/+3
2023-01-20hw/riscv/spike.c: simplify create_fdt()Daniel Henrique Barboza1-3/+1
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza1-2/+1
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_initrd()Daniel Henrique Barboza1-2/+1
2023-01-20hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()Daniel Henrique Barboza1-4/+5
2023-01-20hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()Daniel Henrique Barboza1-8/+2
2023-01-20hw/riscv/spike.c: load initrd right after riscv_load_kernel()Daniel Henrique Barboza1-16/+15
2023-01-20hw/riscv/spike: use 'fdt' from MachineStateDaniel Henrique Barboza1-7/+5
2023-01-20hw/riscv: spike: Decouple create_fdt() dependency to ELF loadingBin Meng1-10/+51
2023-01-20hw/riscv/boot.c: introduce riscv_default_firmware_name()Daniel Henrique Barboza1-9/+5
2023-01-20hw/riscv: spike: Remove the out-of-date commentsBin Meng1-5/+0
2023-01-20hw/char: riscv_htif: Move registers from CPUArchState to HTIFStateBin Meng1-2/+1
2023-01-20hw/char: riscv_htif: Drop useless assignment of memory regionBin Meng1-3/+2
2023-01-06hw/riscv: spike: Remove misleading commentsBin Meng1-1/+0
2022-10-17hw/riscv: set machine->fdt in spike_board_init()Daniel Henrique Barboza1-0/+6
2022-09-07hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()Daniel Henrique Barboza1-1/+1
2022-05-24hw/riscv: Make CPU config error handling generous (virt/spike)Tsukasa OI1-1/+1
2022-04-29hw/riscv: Don't add empty bootargs to device treeBin Meng1-1/+1
2022-04-29hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionallyBin Meng1-2/+3
2022-01-21hw/riscv: Remove macros for ELF BIOS image namesAnup Patel1-2/+2
2022-01-21hw/riscv: spike: Allow using binary firmware as biosAnup Patel1-16/+25
2021-10-22hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel1-5/+9
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel1-1/+1
2021-08-26arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell1-1/+0
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng1-4/+2
2021-06-08hw/riscv: Support the official CLINT DT bindingsBin Meng1-1/+5
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth1-1/+0
2021-03-09qtest: delete superfluous inclusions of qtest.hChen Qun1-1/+0
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng1-6/+3
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis1-4/+4
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis1-4/+4
2020-12-17hw/riscv: spike: Remove compile time XLEN checksAlistair Francis1-21/+24
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis1-1/+2
2020-12-17riscv: spike: Remove target macro conditionalsAlistair Francis1-1/+1
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis1-3/+8
2020-09-09hw/riscv: Move riscv_htif model to hw/charBin Meng1-1/+1
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng1-1/+1
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng1-1/+2
2020-08-25hw/riscv: spike: Allow creating multiple NUMA socketsAnup Patel1-74/+158
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel1-1/+1
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