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2023-03-01
RISC-V: XTheadMemPair: Remove register restrictions for store-pair
Christoph Müllner
1
-4
/
+0
2023-03-01
target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages
Shaobo Song
1
-1
/
+1
2023-03-01
Merge patch series "target/riscv: Various fixes to gdbstub and CSR access"
Palmer Dabbelt
2
-240
/
+201
2023-03-01
target/riscv: Group all predicate() routines together
Bin Meng
1
-90
/
+87
2023-03-01
target/riscv: Drop priv level check in mseccfg predicate()
Bin Meng
1
-1
/
+1
2023-03-01
target/riscv: Allow debugger to access sstc CSRs
Bin Meng
1
-5
/
+14
2023-03-01
target/riscv: Allow debugger to access {h, s}stateen CSRs
Bin Meng
1
-2
/
+20
2023-03-01
target/riscv: Allow debugger to access seed CSR
Bin Meng
1
-0
/
+4
2023-03-01
target/riscv: Allow debugger to access user timer and counter CSRs
Bin Meng
1
-0
/
+4
2023-03-01
target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml
Bin Meng
1
-75
/
+0
2023-03-01
target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()
Bin Meng
1
-0
/
+9
2023-03-01
target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64
Bin Meng
1
-15
/
+9
2023-03-01
target/riscv: Simplify getting RISCVCPU pointer from env
Bin Meng
1
-24
/
+12
2023-03-01
target/riscv: Simplify {read, write}_pmpcfg() a little bit
Bin Meng
1
-2
/
+2
2023-03-01
target/riscv: Use 'bool' type for read_only
Bin Meng
1
-1
/
+1
2023-03-01
target/riscv: Coding style fixes in csr.c
Bin Meng
1
-30
/
+32
2023-03-01
target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
Bin Meng
1
-3
/
+6
2023-03-01
target/riscv: gdbstub: Minor change for better readability
Bin Meng
1
-2
/
+2
2023-03-01
target/riscv: Use g_assert() for the predicate() NULL check
Bin Meng
1
-5
/
+1
2023-03-01
target/riscv: Add some comments to clarify the priority policy of riscv_csrrw...
Bin Meng
1
-1
/
+10
2023-03-01
target/riscv: gdbstub: Check priv spec version before reporting CSR
Bin Meng
1
-0
/
+3
2023-03-01
Merge patch series "target/riscv: Some updates to float point related extensi...
Palmer Dabbelt
6
-170
/
+146
2023-03-01
Merge patch series "make write_misa a no-op and FEATURE_* cleanups"
Palmer Dabbelt
9
-66
/
+39
2023-03-01
target/riscv: Expose properties for Zv* extensions
Weiwei Li
1
-0
/
+7
2023-03-01
target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc
Weiwei Li
1
-8
/
+4
2023-03-01
target/riscv: Fix check for vector load/store instructions when EEW=64
Weiwei Li
1
-5
/
+4
2023-03-01
target/riscv: Add support for Zvfh/zvfhmin extensions
Weiwei Li
1
-2
/
+29
2023-03-01
target/riscv: Remove redundunt check for zve32f and zve64f
Weiwei Li
1
-107
/
+21
2023-03-01
target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc
Weiwei Li
1
-4
/
+4
2023-03-01
target/riscv: Simplify check for Zve32f and Zve64f
Weiwei Li
3
-9
/
+4
2023-03-01
target/riscv: Indent fixes in cpu.c
Weiwei Li
1
-22
/
+22
2023-03-01
target/riscv: Add property check for Zvfh{min} extensions
Weiwei Li
1
-0
/
+14
2023-03-01
target/riscv: Fix relationship between V, Zve*, F and D
Weiwei Li
1
-3
/
+18
2023-03-01
target/riscv: Add cfg properties for Zv* extensions
Weiwei Li
1
-0
/
+3
2023-03-01
target/riscv: Simplify the check for Zfhmin and Zhinxmin
Weiwei Li
1
-13
/
+12
2023-03-01
target/riscv: Fix the relationship between Zhinxmin and Zhinx
Weiwei Li
1
-2
/
+5
2023-03-01
target/riscv: Fix the relationship between Zfhmin and Zfh
Weiwei Li
1
-1
/
+5
2023-03-01
target/riscv/cpu: remove CPUArchState::features and friends
Daniel Henrique Barboza
2
-15
/
+2
2023-03-01
target/riscv: remove RISCV_FEATURE_MMU
Daniel Henrique Barboza
6
-16
/
+5
2023-03-01
hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus()
Daniel Henrique Barboza
1
-3
/
+4
2023-03-01
target/riscv: remove RISCV_FEATURE_PMP
Daniel Henrique Barboza
7
-11
/
+5
2023-03-01
target/riscv: remove RISCV_FEATURE_EPMP
Daniel Henrique Barboza
4
-11
/
+6
2023-03-01
target/riscv/cpu.c: error out if EPMP is enabled without PMP
Daniel Henrique Barboza
1
-2
/
+7
2023-03-01
target/riscv: remove RISCV_FEATURE_DEBUG
Daniel Henrique Barboza
5
-10
/
+4
2023-03-01
target/riscv: allow MISA writes as experimental
Daniel Henrique Barboza
3
-2
/
+8
2023-03-01
target/riscv: do not mask unsupported QEMU extensions in write_misa()
Daniel Henrique Barboza
1
-3
/
+0
2023-03-01
target/riscv: introduce riscv_cpu_cfg()
Daniel Henrique Barboza
1
-0
/
+5
2023-02-28
Merge tag 'buildsys-qom-qdev-ui-20230227' of https://github.com/philmd/qemu i...
Peter Maydell
173
-1966
/
+2183
2023-02-27
ui/cocoa: user friendly characters for release mouse
Christian Schoenebeck
1
-2
/
+5
2023-02-27
dump: Add create_win_dump() stub for non-x86 targets
Philippe Mathieu-Daudé
3
-5
/
+6
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