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authorBin Meng <bmeng@tinylab.org>2023-02-28 21:45:30 +0800
committerPalmer Dabbelt <palmer@rivosinc.com>2023-03-01 16:40:21 -0800
commitfb517fdb150b71d6fad8e2332c9aace82143e45f (patch)
tree637c87d7b3b6d9e2d54bcf769f3ad74246a17eb1
parent7eac8f4191561492fa9fa1e12c80fe27d9842fc6 (diff)
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target/riscv: Allow debugger to access user timer and counter CSRs
At present user timer and counter CSRs are not reported in the CSR XML hence gdb cannot access them. Fix it by adding a debugger check in their predicate() routine. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-14-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
-rw-r--r--target/riscv/csr.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 7284fd8..10ae5df 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -131,6 +131,10 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
skip_ext_pmu_check:
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+
if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) {
return RISCV_EXCP_ILLEGAL_INST;
}