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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-15 10:05:33 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 15:17:51 -0800 |
| commit | 3f4a5a5314b1d2d1fe910b87a3784743993003da (patch) | |
| tree | e893e0fc71a20e6756837682d19e9db87d40acc7 | |
| parent | 51f33081efd4cf3182bf905096888861814522a7 (diff) | |
| download | qemu-3f4a5a5314b1d2d1fe910b87a3784743993003da.zip qemu-3f4a5a5314b1d2d1fe910b87a3784743993003da.tar.gz qemu-3f4a5a5314b1d2d1fe910b87a3784743993003da.tar.bz2 | |
target/riscv: Simplify check for Zve32f and Zve64f
V/Zve64f depend on Zve32f, so we can only check Zve32f in these cases.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-9-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| -rw-r--r-- | target/riscv/cpu_helper.c | 2 | ||||
| -rw-r--r-- | target/riscv/csr.c | 3 | ||||
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 8 |
3 files changed, 4 insertions, 9 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3a9472a..a24a9fd 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -51,7 +51,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base = 0; - if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { + if (cpu->cfg.ext_zve32f) { /* * If env->vl equals to VLMAX, we can use generic vector operation * expanders (GVEC) to accerlate the vector operations. diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1b0a0c1..5b757c8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -93,8 +93,7 @@ static RISCVException vs(CPURISCVState *env, int csrno) CPUState *cs = env_cpu(env); RISCVCPU *cpu = RISCV_CPU(cs); - if (env->misa_ext & RVV || - cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { + if (cpu->cfg.ext_zve32f) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_vector_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index bbb5c3a..6f7ecf1 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -173,9 +173,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2) { TCGv s1, dst; - if (!require_rvv(s) || - !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f || - s->cfg_ptr->ext_zve64f)) { + if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) { return false; } @@ -210,9 +208,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2) { TCGv dst; - if (!require_rvv(s) || - !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f || - s->cfg_ptr->ext_zve64f)) { + if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) { return false; } |