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author | Bin Meng <bmeng@tinylab.org> | 2023-02-28 18:40:24 +0800 |
---|---|---|
committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 16:40:16 -0800 |
commit | 77ad639cb1269ed19fe726edee7c20487b95f7d3 (patch) | |
tree | 1290361aadb6def2258bc052324746de5a4b4bec | |
parent | a7e407b3f87329be533570351fc1658a7ba7b06f (diff) | |
download | qemu-77ad639cb1269ed19fe726edee7c20487b95f7d3.zip qemu-77ad639cb1269ed19fe726edee7c20487b95f7d3.tar.gz qemu-77ad639cb1269ed19fe726edee7c20487b95f7d3.tar.bz2 |
target/riscv: Simplify {read, write}_pmpcfg() a little bit
Use the register index that has already been calculated in the
pmpcfg_csr_{read,write} call.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-9-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
-rw-r--r-- | target/riscv/csr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9264db6..a3e0e57 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3360,7 +3360,7 @@ static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, if (!check_pmp_reg_index(env, reg_index)) { return RISCV_EXCP_ILLEGAL_INST; } - *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); + *val = pmpcfg_csr_read(env, reg_index); return RISCV_EXCP_NONE; } @@ -3372,7 +3372,7 @@ static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, if (!check_pmp_reg_index(env, reg_index)) { return RISCV_EXCP_ILLEGAL_INST; } - pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); + pmpcfg_csr_write(env, reg_index, val); return RISCV_EXCP_NONE; } |