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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-15 10:05:27 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 14:57:23 -0800 |
| commit | a0d805f035ff7132949a4a7e82d7742c243927ed (patch) | |
| tree | a6a5035584940d8e5218d908d6b5be5a698ea39c | |
| parent | 1d2cb5a8689f6c087b297723179676132d1cab32 (diff) | |
| download | qemu-a0d805f035ff7132949a4a7e82d7742c243927ed.zip qemu-a0d805f035ff7132949a4a7e82d7742c243927ed.tar.gz qemu-a0d805f035ff7132949a4a7e82d7742c243927ed.tar.bz2 | |
target/riscv: Fix the relationship between Zhinxmin and Zhinx
Just like zfh and zfhmin, Zhinxmin is part of Zhinx so Zhinxmin
will be enabled when Zhinx is enabled.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-3-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| -rw-r--r-- | target/riscv/cpu.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a717f5d..dcd85f7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -754,8 +754,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) } /* Set the ISA extensions, checks should have happened above */ - if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || - cpu->cfg.ext_zhinxmin) { + if (cpu->cfg.ext_zhinx) { + cpu->cfg.ext_zhinxmin = true; + } + + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) { cpu->cfg.ext_zfinx = true; } |