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7 days[RISCV] Add MC layer support for Andes XAndesVSIntH extension. (#159514)Rux1241-0/+1
Add MC layer support for Andes XAndesVSIntH extension. The spec is available at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release
10 days[RISCV] Implement MC support for Zvfofp8min extension (#157014)Jim Lin1-0/+1
This patch adds MC support for Zvfofp8min https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfofp8min.adoc.
2025-09-12[RISCV][MC] Add MC support of Zibi experimental extension (#127463)Boyao Wang1-0/+1
This adds the MC support of Zibi v0.1 experimental extension. References: * https://lf-riscv.atlassian.net/wiki/spaces/USXX/pages/599261201/Branch+with+Immediate+Zibi+Ratification+Plan * https://lf-riscv.atlassian.net/browse/RVS-3828 * https://github.com/riscv/zibi/releases/tag/v0.1.0
2025-09-11[RISCV] Make "target-feature +i" explicit (#157835)Gergely Futo1-6/+7
Add "target-feature +i" for RV32I/RV64I. Current behavior: RV32E/RV64E: "target-feature +e" "target-feature -i" RV32I/RV64I: "target-feature -e" Adding "target-feature +i" explicitly makes the behavior consistent.
2025-09-01[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc ↵UmeshKalappa1-0/+1
for MIPS RV64 P8700. (#155747) Please refer the https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf for more information . and files like RISCVInstrInfoXMips.td clang formatted . No Regression found. --------- Co-authored-by: Craig Topper <craig.topper@sifive.com>
2025-08-28[RISCV] Implement MC support for Zvfbfa extension (#151106)Jim Lin1-0/+1
This patch adds MC support for Zvfbfa https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfbfa.adoc Since Zvfbfa implies Zve32f, vector floating-point instructions can be used directly with Zvfbfa extension.
2025-08-20[RISCV] Support Remaining P Extension Instructions for RV32/64 (#150379)Qihan Cai1-1/+1
This patch implements pages 15-17 from jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf Documentation: jhauser.us/RISCV/ext-P/RVP-baseInstrs-014.pdf jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf
2025-08-18[RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (#151706)林克1-0/+1
The full spec can be found at spacemit-x60 processor support scope: Section 2.1.2.2 (Features): https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1 This patch only supports assembler.
2025-08-15[RISCV] Remove experimental from Smctr and Ssctr. (#153903)Craig Topper1-2/+2
These extensions were ratified in November 2024.
2025-07-15[RISCV] Add Andes XAndesBFHCvt (Andes Scalar BFLOAT16) extension (#148563)Jim Lin1-0/+1
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. The extension includes only two instructions: one for converting from f32 to f16, and another for converting from f16 to f32. This patch only implements MC support for XAndesBFHCvt.
2025-07-07[RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (#147005)Jim Lin1-0/+1
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only implements MC support for XAndesVSIntLoad. --------- Co-authored-by: Lino Hsing-Yu Peng <linopeng@andestech.com>
2025-07-03[RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)UmeshKalappa1-0/+1
the extension enabled with xmipscbop. Please refer "MIPS RV64 P8700/P8700-F Multiprocessing System Programmer’s Guide" for more info on the extension at https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
2025-06-18[RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension ↵Jim Lin1-0/+1
(#144320) The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. The instructions are similar to `Zvfbfmin` and the only difference with `Zvfbfmin` is that `XAndesVBFHCvt` doesn't have mask variant.
2025-06-16[RISCV] Xqccmp v0.3 (#137854)Sam Elliott1-3/+3
All the changes for v0.2 and v0.3 are either already implemented, or irrelevant to the compiler implementation.
2025-06-16[RISCV] Update Xqci to v0.13.0 (#144398)Sam Elliott1-5/+5
2025-05-30[RISCV] Add shlcofideleg extension (#141572)Ying Chen1-0/+1
This is for `shlcofideleg` extension, that supports delegating LCOFI interrupts to VS-mode. Spec: https://github.com/riscv/riscv-isa-manual/blob/main/src/hypervisor.adoc
2025-05-21[RISCV] Add MC layer support for XSfmm*. (#133031)Craig Topper1-0/+10
This adds assembler/disassembler support for XSfmmbase 0.6 and related SiFive matrix multiplication extensions based on the spec here https://www.sifive.com/document-file/xsfmm-matrix-extensions-specification Functionality-wise, this is the same as the Zvma extension proposal that SiFive shared with the Attached Matrix Extension Task Group. The extension names and instruction mnemonics have been changed to use vendor prefixes. Note this is a non-conforming extension as the opcodes used here are in the standard opcode space in OP-V or OP-VE. --------- Co-authored-by: Brandon Wu <brandon.wu@sifive.com>
2025-05-15[RISCV][MC] Add support for Q extension (#139369)Iris Shi1-0/+1
Closes #130217. https://github.com/riscv/riscv-isa-manual/blob/main/src/q-st-ext.adoc
2025-05-15[RISCV] Add Andes XAndesVDot (Andes Vector Dot Product) extension. (#139849)Jim Lin1-0/+1
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. Intrinsics support will be added in a later patch.
2025-05-13[RISCV] Xqci Extensions v0.11.0 (#137881)Sam Elliott1-14/+14
This updates all the extensions to their version in the v0.11.0 spec. All changes from this version are already implemented or are not relevant to LLVM. This change also alphabetises the lists of Xqci extensions, to make future checks easier, and removes irrelevant info from the usage docs.
2025-05-12[RISCV] Add Andes XAndesVPackFPH (Andes Vector Packed FP16) extension. (#138827)Jim Lin1-0/+1
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. Intrinsics support will be added in a later patch.
2025-04-28[RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)Jim Lin1-0/+1
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. Relocation and fixup for the branch and gp-implied instructions will be added in a later patch.
2025-04-27[RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` (#136842)Pengcheng Wang1-0/+8
This matches GCC and we supported it in LLVM 17/18. Fixes #136803
2025-04-25[RISCV] SiFive CLIC Support (#132481)Sam Elliott1-0/+2
This Change adds support for two SiFive vendor attributes in clang: - "SiFive-CLIC-preemptible" - "SiFive-CLIC-stack-swap" These can be given together, and can be combined with "machine", but cannot be combined with any other interrupt attribute values. These are handled primarily in RISCVFrameLowering: - "SiFive-CLIC-stack-swap" entails swapping `sp` with `sf.mscratchcsw` at function entry and exit, which holds the trap stack pointer. - "SiFive-CLIC-preemptible" entails saving `mcause` and `mepc` before re-enabling interrupts using `mstatus`. To save these, `s0` and `s1` are first spilled to the stack, and then the values are read into these registers. If these registers are used in the function, their values will be spilled a second time onto the stack with the generic callee-saved-register handling. At the end of the function interrupts are disabled again before `mepc` and `mcause` are restored. This Change also adds support for the following two experimental extensions, which only contain CSRs: - XSfsclic - for SiFive's CLIC Supervisor-Mode CSRs - XSfmclic - for SiFive's CLIC Machine-Mode CSRs The latter is needed for interrupt support. The CFI information for this implementation is not correct, but I'd prefer to correct this in a follow-up. While it's unlikely anyone wants to unwind through a handler, the CFI information is also used by debuggers so it would be good to get it right. Co-authored-by: Ana Pazos <apazos@quicinc.com>
2025-04-25[RISCV] Add support for Ziccamoc (#136694)T-Tie1-0/+1
Support for Ziccamoc is added in this pr. Specification link: https://drive.google.com/file/d/12QKRm92cLcEk8-5J9NI91m0fAQOxqNAq/view --------- Co-authored-by: Tie <Tie@llvm.com>
2025-04-22[RISCV] Add smcntrpmf extension (#136556)Liao Chunyu1-0/+1
spec: https://github.com/riscvarchive/riscv-smcntrpmf
2025-04-21[RISCV] Report error if Zilsd is used on RV64. (#136577)Craig Topper1-0/+10
Fixes #136564.
2025-04-15[RISCV] Fix xmipscmov extension name (#135647)Djordje Todorovic1-1/+1
The right name was used in riscv-toolchain-conventions docs.
2025-03-28[RISCV] Add Qualcomm uC Xqciio (External Input Output) extension (#132721)quic_hchandel1-3/+4
This extension adds two external input output instructions for non-memory-mapped device. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
2025-03-24[RISCV] Remove experimental from Sdext and Sdtrig which are ratified. (#132529)Craig Topper1-2/+2
They were ratified in February 2025.
2025-03-22[RISCV] Implement the implications of C extension (#132259)Jesse Huang1-6/+13
Implement the following implications according to the [Zc spec](https://github.com/riscvarchive/riscv-code-size-reduction/blob/main/Zc-specification/Zc.adoc#13-c) > As C defines the same instructions as Zca, Zcf and Zcd, the rule is that: > * C always implies Zca > * C+F implies Zcf (RV32 only) > * C+D implies Zcd
2025-03-22Recommit "[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)" ↵Sudharsan Veeravalli1-1/+2
(#132520) With a minor fix for the build failures. Original message: This extension adds nine instructions, eight for non-memory-mapped devices synchronization and delay instruction. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli quic_svs@quicinc.com
2025-03-21Revert "[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)"Kazu Hirata1-2/+1
This reverts commit 3840f787a21a66686f5d8bf61877d41f3a65f205. Multiple builtbot failures have been reported: https://github.com/llvm/llvm-project/pull/132184
2025-03-22[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)quic_hchandel1-1/+2
This extension adds nine instructions, eight for non-memory-mapped devices synchronization and delay instruction. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
2025-03-20[RISCV] Add assembler support for Zvqdotq. (#132118)Craig Topper1-0/+1
Based on the 0.0.1 spec here https://github.com/riscv/riscv-dot-product/releases/tag/v0.0.1
2025-03-20[RISCV] Add Qualcomm uC Xqcilb (Long Branch) extension (#131996)quic_hchandel1-1/+3
This extension adds two long branch instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
2025-03-19[RISCV] Add Zilsd and Zclsd Extensions (#131094)dong-miao1-0/+7
This commit adds the Load/Store pair instructions (Zilsd) and Compressed Load/Store pair instructions (Zclsd). [Specification link](https://github.com/riscv/riscv-isa-manual/blob/main/src/zilsd.adoc).
2025-03-18[RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (#128833)Sudharsan Veeravalli1-1/+2
This extension adds 10 instructions that provide hints to the interface simulation environment. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/ This patch adds assembler only support.
2025-03-18[RISCV] Add Qualcomm uC Xqcibi (Branch Immediate) extension (#130779)quic_hchandel1-2/+3
This extension adds twelve conditional branch instructions that use an immediate operand for the source. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
2025-03-13[RISCV] Add Qualcomm uC Xqcili (load large immediates) extension (#130012)u4f31-1/+3
The Xqcili extension includes a two instructions that load large immediates than is available with the base RISC-V ISA. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support.
2025-03-12[RISCV] Add an error that Xqccmp, Xqciac, and Xqcicm are not compatible with ↵Craig Topper1-0/+8
C+D or Zcd. (#130816) I was reviewing encodings to put the disassembling of vendor instructions after after standard instructions and found that these overlap with c.fldsp and c.fsdsp.
2025-03-11[RISCV] Update to Xqciint v0.4 (#130219)Sam Elliott1-2/+2
The Xqci 0.7.0 spec just came out, with some updates to Xqciint, bringing it to v0.4. The main update of any relevance is that `qc.c.mienter` and `qc.c.mienter.nest` now update both the stack pointer and the frame pointer (before, they only updated the stack pointer). They both remain compatible with the frame pointer convention. This change bumps the Xqciint version, and ensures that we don't emit the unneeded frame pointer adjustment instruction after `qc.c.mienter(.nest)`.
2025-03-06[RISCV] Add Qualcomm uC Xqcibm (Bit Manipulation) extension (#129504)users/mariusz-sikora-at-amd/testquic_hchandel1-1/+2
This extension adds thirty eight bit manipulation instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.6 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
2025-02-26[RISCV] Add Xqccmp 0.1 Assembly Support (#128731)Sam Elliott1-0/+6
Xqccmp is a new spec by Qualcomm that makes a vendor-specific effort to solve the push/pop + frame pointers issue. Broadly, it takes the Zcmp instructions and reverse the order they push/pop registers in, which ends up matching the frame pointer convention. This extension adds a new instruction not present in Zcmp, `qc.cm.pushfp`, which will set `fp` to the incoming `sp` value after it has pushed the registers. This change duplicates the Zcmp implementation, with minor changes to mnemonics (for the `qc.` prefix), predicates, and the addition of `qc.cm.pushfp`. There is also new logic to prevent combining Xqccmp and Zcmp. Xqccmp is kept separate to Xqci for decoding/encoding etc, as the specs are separate today. Specification: https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0
2025-02-26[RISCV][MC] Add assembler support for XRivosVisni (#128773)Philip Reames1-0/+1
This implements assembler support for the XRivosVisni custom/vendor extension from Rivos Inc. which is defined in: https://github.com/rivosinc/rivos-custom-extensions (See src/xrivosvisni.adoc) Codegen support will follow in separate changes.
2025-02-26[RISCV] Xqcia 0.4 The spec was recently updated, this changes the name in ↵Luke Quinn1-2/+2
the TD files associated and increments the Extension number in the clang driver. This is mostly a MC change as there is no other generated code for these instructions yet. Signed-off-by: Luke Quinn <quic_lquinn@quicinc.com>
2025-02-24[RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (#124706)quic_hchandel1-1/+2
This extension adds eight 48 bit large arithmetic instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support.
2025-02-21[RISCV] Assembler support for XRivosVizip (#127694)Philip Reames1-0/+1
This implements assembler support for the XRivosVizip custom/vendor extension from Rivos Inc. which is defined in: https://github.com/rivosinc/rivos-custom-extensions (See src/xrivosvizip.adoc) Codegen support will follow in a separate change.
2025-02-15[RISCV] Support Zb*/P Shared Instructions (#127160)realqhc1-0/+1
This enables shared instructions between Zb* and Base-P extension. Documentation: https://jhauser.us/RISCV/ext-P/RVP-baseInstrs-014.pdf https://jhauser.us/RISCV/ext-P/RVP-instrEncodings-014.pdf
2025-01-28[RISCV] Add MIPS extensions (#121394)Djordje Todorovic1-0/+2
Adding two extensions for MIPS p8700 CPU: 1. cmove (conditional move) 2. lsp (load/store pair) The official product page here: https://mips.com/products/hardware/p8700
generated by cgit v1.1 at 2025-09-29 18:46:30 +0000