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| author | Jim Lin <jim@andestech.com> | 2025-04-28 17:23:51 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-28 17:23:51 +0800 |
| commit | 6ba1a62a6c512e32bf85f21b59b2c8e507d1a72e (patch) | |
| tree | b1d511c418aab335f72ebb57ffdb17213588be7e /llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | |
| parent | 5afe9c72e4bea2ea38beb1cb0d3a3edc9a958414 (diff) | |
| download | llvm-6ba1a62a6c512e32bf85f21b59b2c8e507d1a72e.zip llvm-6ba1a62a6c512e32bf85f21b59b2c8e507d1a72e.tar.gz llvm-6ba1a62a6c512e32bf85f21b59b2c8e507d1a72e.tar.bz2 | |
[RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)
The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.
This patch only supports assembler.
Relocation and fixup for the branch and gp-implied instructions will be
added in a later patch.
Diffstat (limited to 'llvm/unittests/TargetParser/RISCVISAInfoTest.cpp')
| -rw-r--r-- | llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 7b059ba..b8d33e8 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1127,6 +1127,7 @@ R"(All available -march extensions for RISC-V svnapot 1.0 svpbmt 1.0 svvptc 1.0 + xandesperf 5.0 xcvalu 1.0 xcvbi 1.0 xcvbitmanip 1.0 |