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path: root/llvm/test/Transforms/LoopVectorize/RISCV
AgeCommit message (Expand)AuthorFilesLines
3 hours[LV] Pre-commit test for sinking the recipe into vector early exit block. nfc...Mel Chen1-0/+104
13 hours[RISCV] Set the reciprocal throughtput cost for division to TTI::TCC_Expensiv...Ryan Buchner1-2/+2
8 days[LV][NFC] Update low trip count tail-folding tests (#176898)David Sherwood1-0/+116
10 days[LV] Add missing coverage for LV cost model code paths.Florian Hahn1-0/+60
12 days[LV] Prevent `extract-lane` generate unused IRs with single vector operand. ...Elvis Wang5-15/+0
13 days[VPlan] Explicitly test EVL recipe has "evl" name. NFCLuke Lau1-6/+6
14 days[VPlan] Replace PhiR operand of ComputeRdxResult with VPIRFlags. (#174026)Florian Hahn1-4/+4
2026-01-13[VPlan] Allow VPInstruction::PtrAdd as a user of EVL (#175506)Luke Lau1-0/+47
2026-01-13[LV][NFC] Follow-up fix for #173262 (#175513)Mel Chen1-7/+6
2026-01-12[VPlan] Remove verifier check that EVL can only be used by VPInstruction with...Luke Lau1-0/+64
2026-01-12[LV] Simplify extract-lane with scalar operand to the scalar value itself. (#...Elvis Wang2-18/+3
2026-01-07[LV] Teach m_One, m_ZeroInt patterns to look through broadcasts (#170159)David Sherwood18-200/+92
2026-01-07[LV][EVL] Add test case for issue #173260. nfc (#173262)Mel Chen1-0/+197
2026-01-07[LV] Conservatively predicate SDiv/SRem (#170818)Shih-Po Hung2-11/+385
2026-01-06Reland [VPlan] Simplify pow-of-2 (mul|udiv) -> (shl|lshr) (#174581)Ramkumar Ramachandra30-235/+235
2026-01-06Revert "[VPlan] Simplify pow-of-2 (mul|udiv) -> (shl|lshr)" (#174559)Alex Bradbury30-218/+251
2026-01-06[VPlan] Simplify pow-of-2 (mul|udiv) -> (shl|lshr) (#172477)Ramkumar Ramachandra30-251/+218
2026-01-06[IR] Split vector.splice into vector.splice.left and vector.splice.right (#17...Luke Lau1-8/+8
2025-12-18[VPlan] Extract reverse operation for reverse accesses (#146525)Mel Chen5-49/+50
2025-12-18[LV][EVL] Add test case for checking debug info when tail folding by EVL. nfc...Mel Chen1-0/+93
2025-12-15[VPlan] Directly unroll VectorPointerRecipe (#168886)Ramkumar Ramachandra1-25/+15
2025-12-08[VPlan] Use nuw when computing {VF,VScale}xUF (#170710)Ramkumar Ramachandra2-19/+19
2025-12-08[VPlan] Use BlockFrequencyInfo in getPredBlockCostDivisor (#158690)Luke Lau1-0/+115
2025-11-29[VPlan] Skip cost verification for loops with EVL gather/scatter.Florian Hahn1-0/+116
2025-11-28[VPlan] Skip uses-scalars restriction if one of ops needs broadcast. (#168246)Florian Hahn1-3/+3
2025-11-27[VPlan] Handle scalar VPWidenPointerInd in convertToConcreteRecipes. (#169338)Florian Hahn1-0/+100
2025-11-27[VPlan] Optimize LastActiveLane to EVL - 1 (#169766)Luke Lau6-39/+7
2025-11-26Reapply "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding....Florian Hahn6-280/+229
2025-11-26Revert "Reapply "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-...Florian Hahn6-229/+280
2025-11-26Reapply "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding....Florian Hahn6-280/+229
2025-11-26[VPlan] Use DL index type consistently for GEPs (#169396)Ramkumar Ramachandra6-124/+124
2025-11-25[VPlan] Include flags in VectorPointerRecipe::printRecipe (#169466)Ramkumar Ramachandra3-14/+14
2025-11-24Reland [VPlan] Handle WidenGEP in narrowToSingleScalars (#167880)Ramkumar Ramachandra1-7/+7
2025-11-21[VPlan] Drop poison-generating flags on induction trunc (#168922)Ramkumar Ramachandra1-24/+24
2025-11-18[VPlan] Hoist loads with invariant addresses using noalias metadata. (#166247)Florian Hahn1-3/+3
2025-11-17Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)Ramkumar Ramachandra15-133/+197
2025-11-14Revert "[VPlan] Expand WidenInt inductions with nuw/nsw" (#168080)Alex Bradbury14-133/+133
2025-11-14[VPlan] Expand WidenInt inductions with nuw/nsw (#163538)Ramkumar Ramachandra14-133/+133
2025-11-14[VPlan] Disable partial reductions again with EVL tail folding (#167863)Luke Lau1-0/+125
2025-11-13Revert "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. ...Florian Hahn6-229/+280
2025-11-13[VPlan] Simplify ExplicitVectorLength(%AVL) -> %AVL when AVL <= VF (#167647)Luke Lau2-18/+13
2025-11-12[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)Florian Hahn6-280/+229
2025-11-12[VPlan] Plumb scalable register size through narrowInterleaveGroups (#167505)Luke Lau1-0/+214
2025-11-12[LV][EVL] Replace VPInstruction::Select with vp.merge for predicated div/rem ...Mel Chen1-18/+3
2025-11-11Revert "[VPlan] Handle WidenGEP in narrowToSingleScalars" (#167509)Ramkumar Ramachandra1-7/+7
2025-11-11[VPlan] Handle WidenGEP in narrowToSingleScalars (#166740)Ramkumar Ramachandra1-7/+7
2025-11-10[VPlan] Permit more users in narrowToSingleScalars (#166559)Ramkumar Ramachandra1-3/+3
2025-11-10[VPlan] Simplify branch-cond with getVectorTripCount (#155604)Ramkumar Ramachandra1-2/+1
2025-11-07[VPlan] Remove no-longer-needed EVL VPlan debug output tests. NFC (#166158)Luke Lau2-1087/+0
2025-11-05[VPlan] Handle single-scalar conds in VPWidenSelectRecipe. (#165506)Florian Hahn2-17/+19
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