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2026-02-12[WebAssembly] Error on Wasm SjLj if +exception-handling is missing (#181070)HEADmainHeejin Ahn6-10/+33
2026-02-12[SeparateConstOffsetFromGEP] Update splitGEP to handle case where including b...Adel Ejjeh1-0/+88
2026-02-12[MemProf] Emit richer optimization remarks for single-type allocations (#181089)Teresa Johnson1-5/+32
2026-02-12[UTC][VPlan] Use `-vplan-print-after` for VPlan-dump-based tests (#178736)Andrei Elovikov10-103/+103
2026-02-12[HWASan][Fuchsia] Have Fuchsia use a dynamic shadow start (#180881)PiJoules2-11/+11
2026-02-12[SLP]Fix crash with deleted non-copyable node in scheduling copyablesAlexey Bataev4-21/+189
2026-02-12[RISCV] Update sched resources used by XSfvcp instructions (#181206)Min-Yih Hsu1-0/+162
2026-02-12[SLP] Use the correct identity when combining binary opcodes with AND/MUL (#1...Ryan Buchner4-3/+114
2026-02-12[AArch64][llvm] Allow FPRCVT insns to run in streaming mode if safe (#177334)Jonathan Thackray2-1915/+220
2026-02-13[InstructionSimplify] Extend simplifyICmpWithZero to handle equivalent zero R...Kunqiu Chen3-14/+222
2026-02-12[AArch64][llvm] Preserve FP_TO_*_SAT VT operand in SVE scalar-combine (#177333)Jonathan Thackray2-0/+3299
2026-02-12[llvm][DebugInfo] Allow anonymous basic types (#180016)Tom Tromey1-0/+23
2026-02-12[VPlan] Explicitly reassociate header mask in logical and (#180898)Luke Lau5-23/+26
2026-02-12[LV] Add LoopVectorize/VPlan subdirectory for VPlan printing tests. (#180611)Florian Hahn38-45/+12
2026-02-12Revert "[IndVarSimplify] Add safety check for getTruncateExpr in genLoopLimit...Nikita Popov1-149/+0
2026-02-12[AggressiveInstCombine] Create zext during store merge (#181125)Nikita Popov1-0/+17
2026-02-12[VPlan] Introduce m_c_Logical(And|Or) (#180048)Ramkumar Ramachandra1-0/+83
2026-02-12[AArch64][ISel] Lower fixed-width i64 vector CLMUL intrinsics (#178876)Matthew Devereau1-629/+648
2026-02-12[AArch64][GlobalISel] Add some extra sqxtn test coverage. NFCDavid Green2-20/+347
2026-02-12[AArch64] Eliminate XTN/SSHLL for vector splats (#180913)Guy David1-0/+119
2026-02-12[AArch64]Add SCR2_EL3 system register (#180918)CarolineConcatto1-0/+24
2026-02-12[AArch64][GlobalISel] Update and regnerate switch-cases-to-branch-and.ll. NFCDavid Green1-543/+438
2026-02-12[SelectionDAG] Make sure demanded lanes for AND/MUL-by-zero are frozen (#180727)Björn Pettersson13-44/+125
2026-02-12[DAGCombiner] Fix subvector extraction index for big-endian STLF (#180795)陈子昂2-2/+29
2026-02-12[AMDGPU] Add missing assert requirement to unit test (#181102)Lucas Ramirez1-0/+1
2026-02-12[AArch64][ISel] Add clmul to pmullb/t lowering (#180568)Matthew Devereau1-707/+1060
2026-02-12[SDAG] Copy flags in convertMask when legalizing vselect/setcc (#180979)David Green1-96/+12
2026-02-12Reapply "[MC][TableGen] Expand Opcode field of MCInstrDesc" (#180321) (#180954)sstipano1-5/+5
2026-02-11[RISCV] Improve 2*XLEN SHL legalization with P extension. (#181056)Craig Topper2-33/+13
2026-02-11[RISCV] Use NSRL/NSRA for legalizing i64 shifts with P extension on RV32. (#1...Craig Topper1-38/+40
2026-02-12[Hexagon] Add support for V128i1/V64i1/V32i1 predicate store/load in HVX (#18...pkarveti1-0/+89
2026-02-12[llvm-dwp] Adds --prioritize-discard-path to explicitly control dwp overflow ...Liu Ke1-0/+41
2026-02-12[llvm-ir2vec] Adding BB Embeddings Map API to ir2vec python bindings (#180135)Nishant Sachdeva1-0/+28
2026-02-11Revert "[MC/DC] Make covmap tolerant of nested Decisions (#125407)" (#181069)gulfemsavrun1-7/+7
2026-02-12[RISCV] Update Andes45 vector fixed-point arithmetic scheduling info (#180451)Jim Lin3-1031/+1031
2026-02-12[AMDGPU][Scheduler] Fix inconsistent MI slots after rematerialization revert ...Lucas Ramirez1-0/+331
2026-02-11[AMDGPU][NFC] Fix test by removing debug flag in llvm.amdgcn.raw.buffer.atomi...Syadus Sefat1-1/+1
2026-02-11[RISC] Rename the P extensions srx/slx tests and add fshl/fshr intrinsic test...Craig Topper2-18/+414
2026-02-11[SLP]Add external uses estimations into tree throttlingAlexey Bataev4-41/+38
2026-02-11[SPIRV] Scalarize single-element vectors in type creation (#180735)Dmitry Sidorov1-0/+53
2026-02-11[LV] Don't scalarize loads that need predication in legacy CM.Florian Hahn1-0/+83
2026-02-11[AMDGPU][ISel] `setcc` peephole for comparisons with upper 32 bits of a 64-bi...zGoldthorpe14-183/+394
2026-02-11[AMDGPU][GlobalIsel] Add register bank legalization rules for buffer atomic i...Syadus Sefat1-0/+282
2026-02-11[AMDGPU] Treat F64 TRANS instructions as VALU for S_DELAY_ALU insertion (#180...Jay Foad4-24/+37
2026-02-11[SLP]Correctly process deleted gathered loads and short treesAlexey Bataev3-384/+329
2026-02-11[LoopUnrollPass] Indent `LLVM_DEBUG()` messages based on our depth in the `tr...Justin Fargnoli1-0/+204
2026-02-11[WebAssembly] Add a WASM table to `llvm/test/MC/WebAssembly/wasm64.s`. NFC (#...Demetrius Kanios1-13/+31
2026-02-11AMDGPU/GlobalISel: RegBankLegalize for global atomic ordered add (#180829)vangthao951-2/+15
2026-02-11[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)vangthao9512-330/+81
2026-02-11[AArch64] Add extra fcmp+select tests. NFCDavid Green1-0/+522
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