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16 hours[AArch64] Align nontemporal store/load little-endian checks (#177468)Tomer Shafir1-65/+115
39 hours[LV] Precommit extra argmin/argmax tests for #170223.Florian Hahn1-0/+43
3 days[LV] Add additional tests for early-exit loops loads not known deref.Florian Hahn1-0/+132
5 days[LV] Separate runtime check cost from total overhead in profitability check (...Mel Chen4-9/+4
7 days[LV] Add replicating load/store cost tests for Apple CPUs.Florian Hahn1-0/+813
8 days[LV] Consider UserIC when limiting VF. (#174573)Florian Hahn1-31/+35
8 days[LV][NFC] Update low trip count tail-folding tests (#176898)David Sherwood1-1/+1
9 days[LV] Add extra tests with sink-able recipes.Florian Hahn2-205/+472
10 daysRecommit "[VPlan] Only use isAddressSCEVForCost in legacy getAddressAccSCEV"Florian Hahn2-24/+41
10 days[VPlan] Match inverted logical AND/OR for select costs.Florian Hahn1-8/+8
11 days[LV] Add missing coverage for LV cost model code paths.Florian Hahn2-24/+276
12 days[LoopVectorize] Support vectorization of overflow intrinsics (#174835)Vishruth Thimmaiah1-1/+73
12 days[LV] Prevent `extract-lane` generate unused IRs with single vector operand. ...Elvis Wang1-3/+0
14 days[LV] Add additional cost and folding test coverage. (NFC)Florian Hahn1-0/+65
14 days[LV] Vectorize conditional scalar assignments (#158088)Graham Hunter2-0/+906
2026-01-14[VPlan] Replace PhiR operand of ComputeRdxResult with VPIRFlags. (#174026)Florian Hahn1-4/+4
2026-01-14[LV] Fix bug in setVectorizedCallDecision (#175742)David Sherwood1-29/+29
2026-01-13[VPlan] Optimize BranchOnTwoConds to chain of 2 simple branches. (#174016)Florian Hahn2-37/+30
2026-01-12[profcheck] Fix encoding of 0 loopEstimatedTrip count (#174896)Mircea Trofin1-5/+5
2026-01-12[AArch64] Define cost of i16->i32 udot/sdot instructions (#174102)Sander de Smalen1-0/+66
2026-01-12[LV] Simplify extract-lane with scalar operand to the scalar value itself. (#...Elvis Wang1-2/+0
2026-01-11[VPlan] Add missing sext(sub) SCEV fold to getSCEVExprForVPValue.Florian Hahn1-0/+255
2026-01-09[AArch64][VecLib] Add vector function mappings for the modf, sincos, sincospi...Paul Osmialowski1-1/+358
2026-01-09Revert "[VPlan] Only use isAddressSCEVForCost in legacy getAddressAccSCEV (NF...Hans Wennborg1-40/+12
2026-01-07[SCEV] Handle URem pattern in getRangeRef. (#174456)Florian Hahn1-14/+7
2026-01-07[LV] Teach m_One, m_ZeroInt patterns to look through broadcasts (#170159)David Sherwood8-68/+40
2026-01-06Reland [VPlan] Simplify pow-of-2 (mul|udiv) -> (shl|lshr) (#174581)Ramkumar Ramachandra62-388/+388
2026-01-06[VPlan] Only use isAddressSCEVForCost in legacy getAddressAccSCEV (NFCI)Florian Hahn1-12/+40
2026-01-06Revert "[VPlan] Simplify pow-of-2 (mul|udiv) -> (shl|lshr)" (#174559)Alex Bradbury62-370/+393
2026-01-06[VPlan] Simplify pow-of-2 (mul|udiv) -> (shl|lshr) (#172477)Ramkumar Ramachandra62-393/+370
2026-01-06[IR] Split vector.splice into vector.splice.left and vector.splice.right (#17...Luke Lau4-17/+17
2026-01-05[LV] Add test case for costs of load of pointer inductions (NFC).Florian Hahn1-0/+72
2026-01-05[VPlan] Remove VPWidenSelectRecipe, use VPWidenRecipe instead (NFCI). (#174234)Florian Hahn1-12/+12
2026-01-04[IR] Reland Optimize PHINode::removeIncomingValue() and PHINode::removeIncomi...Mingjie Xu1-3/+3
2026-01-02[AArch64] Turn MaxInterleaveFactor into a subtarget feature (#171088)David Green1-92/+204
2025-12-30[LV] Add extra tests for computing replicating cast costs (NFC)Florian Hahn2-25/+198
2025-12-29Revert 159f1c048e08a8780d92858cfc80e723c90235e3 (#173893)Walter Lee1-3/+3
2025-12-29[VPlan] Add BranchOnTwoConds, use for early exit plans. (#172750)Florian Hahn1-2/+2
2025-12-22Reapply "[VPlan] Use predicate from VPValue VPWidenSelectR::computeCost." (#1...Florian Hahn1-4/+4
2025-12-22[LV] Add additional select cost test with live-in compare cond (NFC).Florian Hahn1-0/+27
2025-12-20Revert "[VPlan] Use predicate from VPValue VPWidenSelectR::computeCost." (#17...Florian Hahn1-4/+4
2025-12-20[VPlan] Use predicate from VPValue VPWidenSelectR::computeCost. (#172915)Florian Hahn1-4/+4
2025-12-19[LV] Check Addr in getAddressAccessSCEV in terms of SCEV expressions. (#171204)Florian Hahn1-21/+214
2025-12-18[LV] Add select cost test with negated condition. (NFC)Florian Hahn1-24/+47
2025-12-18[VPlan] Extract reverse operation for reverse accesses (#146525)Mel Chen2-2/+2
2025-12-17[IR] Optimize PHINode::removeIncomingValue() by swapping removed incoming val...Mingjie Xu1-3/+3
2025-12-16[VPlan] Replace BranchOnCount with Compare + BranchOnCond (NFC). (#172181)Florian Hahn1-1/+2
2025-12-16Reapply "[VPlan] Remove legacy costing inside VPBlendRecipe::computeCost (#17...Luke Lau1-0/+88
2025-12-15[VPlan] Directly unroll VectorPointerRecipe (#168886)Ramkumar Ramachandra32-1010/+767
2025-12-11[LV] Always include middle block cost in isOutsideLoopWorkProfitable. (#171102)Florian Hahn4-10/+11
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