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path: root/llvm/test/Transforms/LoopVectorize/AArch64
AgeCommit message (Expand)AuthorFilesLines
2026-02-13[InstructionSimplify] Extend simplifyICmpWithZero to handle equivalent zero R...Kunqiu Chen1-8/+8
2026-02-12[VPlan] Explicitly reassociate header mask in logical and (#180898)Luke Lau1-9/+11
2026-02-12[LV] Add LoopVectorize/VPlan subdirectory for VPlan printing tests. (#180611)Florian Hahn4-663/+0
2026-02-11[LAA] Use SCEVPtrToAddr in tryToCreateDiffChecks. (#178861)Florian Hahn13-64/+64
2026-02-10[VPlan] Reject partial reductions with invalid costs in getScaledReds. (#180438)Florian Hahn1-0/+95
2026-02-10[LV] Handle partial sub-reductions with sub in middle block. (#178919)Sander de Smalen3-24/+102
2026-02-10Reland "[LV] Support conditional scalar assignments of masked operations" (#1...Benjamin Maxwell1-0/+1144
2026-02-09[LV] Add additional tests for reductions with intermediate stores. (NFC)Florian Hahn1-3/+69
2026-02-09[VPlan] Simplify single-entry VPWidenPHIRecipe.Florian Hahn1-4/+3
2026-02-09Reland "[LoopVectorize] Support vectorization of overflow intrinsics" (#180526)Vishruth Thimmaiah1-1/+73
2026-02-09[VPlan] Skip applying InstsToScalarize with forced instr costs. (#168269)Florian Hahn1-0/+75
2026-02-06Revert "[LV] Support conditional scalar assignments of masked operations" (#1...Kewen Meng1-1144/+0
2026-02-06[LV] Support conditional scalar assignments of masked operations (#178862)Benjamin Maxwell1-0/+1144
2026-02-05[AArch64] Add FeatureUseFixedOverScalableIfEqualCost to Neoverse-V3 and Neove...David Green3-209/+7
2026-02-05Revert "[LoopVectorize] Support vectorization of overflow intrinsics" (#179819)Alexander Kornienko1-73/+1
2026-02-03[VPlan] Refine exit select check in transformtoPartialReduction.Florian Hahn1-0/+54
2026-02-03[VPlan] Sink recipes from the vector loop region in licm. (#168031)Mel Chen6-95/+108
2026-01-30[LV] Add additional partial reduction test coverage for #167851.Florian Hahn3-113/+228
2026-01-30[VPlan] Mark VPActiveLaneMaskPHIRecipe as readnone. (#177886)Florian Hahn3-31/+85
2026-01-30NFC: Cleanup AArch64/partial-reduce-chained.llSander de Smalen1-15/+16
2026-01-30[LV] Add support for extended fadd reductions (#178447)Sander de Smalen1-0/+141
2026-01-28[LV] Add support for llvm.vector.partial.reduce.fadd (#163975)Damian Heaton1-0/+757
2026-01-27[AArch64] Align nontemporal store/load little-endian checks (#177468)Tomer Shafir1-65/+115
2026-01-26[LV] Precommit extra argmin/argmax tests for #170223.Florian Hahn1-0/+43
2026-01-25[LV] Add additional tests for early-exit loops loads not known deref.Florian Hahn1-0/+132
2026-01-23[LV] Separate runtime check cost from total overhead in profitability check (...Mel Chen4-9/+4
2026-01-21[LV] Add replicating load/store cost tests for Apple CPUs.Florian Hahn1-0/+813
2026-01-20[LV] Consider UserIC when limiting VF. (#174573)Florian Hahn1-31/+35
2026-01-20[LV][NFC] Update low trip count tail-folding tests (#176898)David Sherwood1-1/+1
2026-01-19[LV] Add extra tests with sink-able recipes.Florian Hahn2-205/+472
2026-01-18Recommit "[VPlan] Only use isAddressSCEVForCost in legacy getAddressAccSCEV"Florian Hahn2-24/+41
2026-01-18[VPlan] Match inverted logical AND/OR for select costs.Florian Hahn1-8/+8
2026-01-17[LV] Add missing coverage for LV cost model code paths.Florian Hahn2-24/+276
2026-01-16[LoopVectorize] Support vectorization of overflow intrinsics (#174835)Vishruth Thimmaiah1-1/+73
2026-01-16[LV] Prevent `extract-lane` generate unused IRs with single vector operand. ...Elvis Wang1-3/+0
2026-01-14[LV] Add additional cost and folding test coverage. (NFC)Florian Hahn1-0/+65
2026-01-14[LV] Vectorize conditional scalar assignments (#158088)Graham Hunter2-0/+906
2026-01-14[VPlan] Replace PhiR operand of ComputeRdxResult with VPIRFlags. (#174026)Florian Hahn1-4/+4
2026-01-14[LV] Fix bug in setVectorizedCallDecision (#175742)David Sherwood1-29/+29
2026-01-13[VPlan] Optimize BranchOnTwoConds to chain of 2 simple branches. (#174016)Florian Hahn2-37/+30
2026-01-12[profcheck] Fix encoding of 0 loopEstimatedTrip count (#174896)Mircea Trofin1-5/+5
2026-01-12[AArch64] Define cost of i16->i32 udot/sdot instructions (#174102)Sander de Smalen1-0/+66
2026-01-12[LV] Simplify extract-lane with scalar operand to the scalar value itself. (#...Elvis Wang1-2/+0
2026-01-11[VPlan] Add missing sext(sub) SCEV fold to getSCEVExprForVPValue.Florian Hahn1-0/+255
2026-01-09[AArch64][VecLib] Add vector function mappings for the modf, sincos, sincospi...Paul Osmialowski1-1/+358
2026-01-09Revert "[VPlan] Only use isAddressSCEVForCost in legacy getAddressAccSCEV (NF...Hans Wennborg1-40/+12
2026-01-07[SCEV] Handle URem pattern in getRangeRef. (#174456)Florian Hahn1-14/+7
2026-01-07[LV] Teach m_One, m_ZeroInt patterns to look through broadcasts (#170159)David Sherwood8-68/+40
2026-01-06Reland [VPlan] Simplify pow-of-2 (mul|udiv) -> (shl|lshr) (#174581)Ramkumar Ramachandra62-388/+388
2026-01-06[VPlan] Only use isAddressSCEVForCost in legacy getAddressAccSCEV (NFCI)Florian Hahn1-12/+40
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